Semiconductor integrated circuit including a first region and a second region
View Patent ↗A semiconductor integrated circuit effectively makes use of wiring channels of wiring formed by a damascene method. When first cells are used, since the M 1 power source lines are laid out at positions spaced away from a boundary between the cells, the power source lines are not combined in laying out a semiconductor integrated circuit. As a result, the width of the power source lines is not changed. Accordingly, an interval between the line and a line which is arranged close to the line, determined in response to a line width of the lines, can satisfy a design rule; and, hence, the reduction of the wiring channels can be obviated, whereby the supply rate of the wiring channels can be enhanced, and, further, the integrity of a semiconductor chip can be enhanced.
1. A semiconductor integrated circuit which is formed on one semiconductor substrate in a form so that the semiconductor integrated circuit includes a first region and a second region, which is different from the first region,
wherein a plurality of first cells having respectively given functions are arranged in the first region, lines which are arranged on peripheral portions of a first cell are laid out at positions away from boundaries of the first cells which are arranged close to each other, and
wherein a plurality of second cells having respectively given functions are arranged in the second region, a second cell includes wide-width lines arranged on the peripheral portion thereof and narrow-width lines having a line width narrower than the line width of the wide-width lines in the second cell, and the line interval between a wide-width line and a narrow-width line, which is arranged close to the wide-width line, is set to be wider than the minimum arrangement pitch of the narrow-width lines.
2. A semiconductor integrated circuit according to claim 1 , wherein the line interval between a wide-width line and a narrow-width line that is arranged close to the wide-width line is formed by omitting the wiring formation on the minimum arrangement pitch of the narrow-width lines.
3. A semiconductor integrated circuit according to claim 1 , wherein the line on the peripheral portion in the first cell is laid out at a position spaced away, by a minimum arrangement pitch of the narrow-width lines, from the boundary between first cells which are arranged close to each other.
4. A semiconductor integrated circuit according to claim 1 , wherein a first cell includes bridging portions which are capable of bridging the wide-width line of one first cell and the wide-width line of another first cell arranged close to the one first cell.
5. A semiconductor integrated circuit device according to claim 1 ,
wherein the lines are formed by embedding a conductive film into grooves formed in an insulating film.
6. A semiconductor integrated circuit device according to claim 5 ,
wherein the conductive film is comprised of copper.
7. A semiconductor integrated circuit device according to claim 1 ,
wherein the lines are comprised of copper.