Deep trench (DT) metal-insulator-metal (MIM) capacitor
View Patent ↗A deep trench metal-insulator-metal (MIM) capacitor in an SOI-type substrate. In the deep trench, a layer of TiN, followed by a layer of high-k dielectric, followed by a second layer of TiN. The resulting capacitor is completely buried below the SOI layer, thereby allowing for subsequent structures to be placed over the deep trench.
1. Method of forming a deep trench metal-insulator-metal (MIM) capacitor in an SOI-type substrate having a layer of silicon (SOI) atop a buried oxide (BOX) layer which is atop an underlying substrate, comprising:
forming a deep trench (DT) extending through the SOI layer and the BOX layer, and into the underlying substrate;
depositing a thin, conformal layer of a first conductive material to serve as a first of two conductive electrodes for a capacitor being formed in the deep trench;
removing a portion of the first conductive material from a top portion of the deep trench, recessing it to below the SOI layer;
depositing a dielectric layer covering sidewalls and a bottom of the deep trench, and the first conductive material;
filling the deep trench with a second conductive material, to serve as a second of the two conductive electrodes for a capacitor being formed in the deep trench; and
recessing the second conductive material so that its top surface is recessed below the SOI layer.
2. The method of claim 1 , wherein:
the underlying substrate is a silicon substrate;
the BOX layer has a thickness of 500-2500 Å; and
the SOI layer has a thickness of 50-200 Å.
3. The method of claim 1 , wherein:
the deep trench (DT) has a depth of 2000-5000 nm and a width of 50-150 nm.
4. The method of claim 1 , wherein:
the first conductive material comprises titanium nitride (TiN).
5. The method of claim 1 , wherein:
the first conductive material has a thickness of 5-10 nm.
6. The method of claim 1 , further comprising:
forming a buried plate in the underlying substrate, surrounding the deep trench.
7. The method of claim 1 , wherein:
the first conductive material is recessed to be above a top surface of the underlying substrate.
8. The method of claim 1 , wherein:
the first conductive material is recessed to be within the underlying substrate.
9. The method of claim 1 , wherein:
the dielectric layer comprises hafnium oxide.
10. The method of claim 1 , wherein:
the dielectric layer has a thickness of 2-6 nm.
11. The method of claim 1 , wherein:
the second conductive material comprises titanium nitride (TiN).
12. The method of claim 1 , wherein:
the second conductive material comprises a thin liner of titanium nitride (TiN) followed by a thick deposition of polysilicon.
13. The method of claim 1 , wherein:
the second conductive material is recessed to that its top surface is between bottom and top surfaces of the BOX layer.
14. The method of claim 1 , further comprising:
etching to expose an underside of the SOI layer.
15. The method of claim 1 , further comprising:
depositing polysilicon and etching it back to form a strap on top of the second conductive material.
16. The method of claim 15 , wherein:
the polysilicon is etched back to below a top surface of the SOI layer and above a bottom surface of the SOI layer.