Method and system for operating a comparator

1. A method of operating a comparator, the method comprising:

analyzing an output of the comparator based on at least one of a transition of the output, present operational state of the comparator, and at least one time instant corresponding to the output wherein the analyzing comprises detecting an occurrence of at least one transition of the output of the comparator, further wherein the transition of the output corresponds to a time instant when inputs to the comparator satisfy a condition which causes the transition of the output of the comparator; and controlling an operational state of the comparator based on the analysis of the output.

2. The method of claim 1 , wherein the operational state of the comparator is one of an enabled state, a disabled state, and a low power state.

3. The method of claim 1 , wherein the comparator operates in one of a disabled state and a low power state based on the occurrence of the transition of the output.

4. The method of claim 1 further comprising determining the time of the occurrence of the at least one transition.

5. The method of claim 4 further comprising predicting at least one time instant corresponding to the at least one transition of the output of the comparator based on the time of occurrence of the at least one transition.

6. The method of claim 5 further comprising computing at least one time interval between the at least one transition of the output, the at least one time instant being predicted based on the at least one time interval.

7. The method of claim 6 , wherein computing the at least one time interval comprises counting a number of cycles of a periodic sampling wave during the time interval.

8. The method of claim 7 , wherein the periodic sampling wave is a quantization clock.

9. The method of claim 7 , wherein the operational state of the comparator is controlled by gating the periodic sampling wave.

10. The method of claim 5 , wherein the comparator operates in an enabled state at a time instant predicted corresponding to the transition of the output of the comparator.

11. The method of claim 5 , wherein the comparator operates in one of a disabled state and a low power state before a time instant predicted corresponding to the transition of the output of the comparator.

12. The method of claim 2 , wherein the comparator operates in at least one of the disabled state and the low power state when the output of the comparator is constant over a time interval.

13. The method of claim 1 , wherein the comparator operates as a Pulse Width Modulated (PWM) Analog to Digital Converter (ADC).

14. A system for comparing a plurality of signals, the system comprising:

a comparator for receiving the plurality of signals, wherein the comparator is enabled at one or more time instants by a periodic sampling wave;

an output analyzing module configured to analyze an output of the comparator wherein the output analyzing module comprises a detecting module configured to detect an occurrence of at least one transition of the output of the comparator, further wherein the transition of the output corresponds to a time instant when inputs to the comparator satisfy a condition which causes the transition of the output of the comparator; and

a control logic module operatively coupled to the comparator, wherein the control logic module controls an operational state of the comparator on at least one time instant based on the analysis of the output of the comparator.

15. The system of claim 14 , wherein the output of the comparator is stored in a latch.

16. The system of claim 15 , wherein the control logic module controls application of the periodic sampling wave to the latch based on the analysis of the output of the comparator.

17. The system of claim 14 further comprising a determining module configured to determine the time of the occurrence of the at least one transition.

18. The system of claim 14 , wherein the output analyzing module further comprises a predicting module to predict at least one time instant corresponding to the time of the occurrence of the at least one transition.

19. The system of claim 18 further comprising a computing module configured to compute at least one time interval between the at least one transition of the output.

20. The system of claim 14 further comprising at least one of:

a counter, wherein the counter is configured to count the number of cycles of a periodic sampling wave between at least one transition of the output of the comparator; and

a register, wherein the register stores at least one result of the counter corresponding to the at least one transition.

21. The system of claim 14 , wherein the system is a Pulse Width Modulated (PWM) Analog to Digital Converter (ADC).

22. The system of claim 14 , wherein the operational state of the comparator is one of an enabled state, a disabled state, and a low power state.

23. The system of claim 21 , wherein the control logic module operates the comparator in one of a disabled state and a low power state on at least one time instant corresponding to each cycle of a predefined clock.

24. The system of claim 14 further comprising an input analyzing module configured to analyze the at least one signal received by the comparator.

25. The system of claim 24 , wherein the input analyzing module is further configured to detect strength of the at least one signal based on the analysis of the at least one signal received by the comparator.

26. The system of claim 23 , wherein the control logic module controls the operational state of the comparator based on the analysis of the at least one signal received by the comparator.

27. The system of claim 24 , wherein the input analyzing module is further configured to detect an occurrence of a condition which causes the transition of the output of the comparator.