Maintaining dynamic count of FIFO contents in multiple clock domains
View Patent ↗Disclosed is a system that generates a write count value for indicating whether data can be read from a FIFO and a system that generates a read count value for indicating whether data can be written to a FIFO. Each of these systems operates in two separate clock domains. In the system that generates a write count value, write strobes are stored in parallel in a register in a first clock domain. The plurality of synchronizers trigger on a rising edge of the write strobe that is stored in the parallel register and generate an increment pulse in a second clock domain. An up/down counter reads the increment pulse in parallel and increments the up/down counter in parallel. A decrement signal from a read strobe decrements the up/down counter. The output of the counter is fed to a register that provides a write counter value to handshake logic that indicates whether data can be read from a FIFO without underflowing the FIFO.
1. A method of generating a write count value in a read clock domain from write strobes generated in a write clock domain indicating an amount of data that is present in a FIFO comprising:
writing said write strobes to sequential storage devices in a parallel register in response to a write clock signal and simultaneously clearing other devices in said parallel register;
transferring data stored in said sequential storage devices to synchronizers in response to said write clock signal;
detecting a leading edge of said data transferred from said sequential storage devices;
generating an increment pulse in said synchronizers in said read clock domain;
applying said increment pulse to an up/down counter in parallel to increment said up/down counter;
decrementing said up/down counter upon receipt of a read strobe pulse;
generating a write counter value in said read clock domain that is indicative of said amount of data that is present in said FIFO.
2. The method of claim 1 wherein said process of writing said write strobes to sequential storage devices in a parallel register comprises sequentially writing said write strobes to a plurality of flip-flops by directing said write strobes through steering logic.
3. The method of claim 2 further comprising:
selecting a number of said flip-flops that form said parallel register as greater than or equal to a number of said write clock pulses that occur from the time when said write strobe is first received until said up/down counter is incremented by said write strobe.
4. A method of generating a read count value in a write clock domain from read strobes generated in a read clock domain indicating a number of open slots present in a FIFO comprising:
writing said read strobes to sequential storage devices in a parallel register in response to a read clock signal and simultaneously clearing other devices in said parallel register;
transferring data stored in said sequential storage devices to synchronizers in response to said read clock signal;
detecting a leading edge of said data transferred from said sequential storage devices;
generating a decrement pulse in said synchronizers in said write clock domain;
applying said decrement pulse to an up/down counter in parallel to decrement said up/down counter;
incrementing said up/down counter upon receipt of a write strobe pulse;
generating a read counter value in said read clock domain that is indicative of said number of open slots that are present in said FIFO.
5. The method of claim 4 wherein said process of writing said read strobes to sequential storage devices in parallel register comprises sequential writing said read strobes to a plurality of flip-flops by directing said read strobes through steering logic.
6. The method of claim 5 further comprising:
selecting said flip-flops that form said parallel register as an amount greater than or equal to a number of said read clock pulses that occur from the time when said read strobe is first received until said up/down counter is decremented by said read strobe.
7. A device for generating a write counter value in a read clock domain to indicate the amount of data that is present in a FIFO comprising:
steering/reset logic that generates a write output pulse in a write clock domain on sequential outputs and simultaneously generates a reset pulse on other outputs;
a parallel register that stores said write output pulse and generates a edge signal in said write clock domain;
synchronizers connected in parallel to said parallel register that detect said rising edge signal and generate increment pulses in said read clock domain;
an up/down counter that receives said increment pulses in parallel and increments said up/down counter in response to said increment pulses, and receives a read strobe pulse and decrements said up/down counter in response to said read strobe pulse, said up/down counter having a counter output that provides a write count signal;
a register that generates a write counter value in said read clock domain that indicates the amount of data that is present in said FIFO.
8. The device of claim 7 wherein said parallel register comprises a predetermined number of flip-flops that are connected in parallel to said steering/reset logic, said predetermined number being greater than or equal to the number of clock pulses in said write clock domain that are required to clock a write pulse from said steering/reset logic to said up/down counter.
9. A device for generating a read counter value in a write clock domain from read strobes generated in a read clock domain to indicate the number of slots open in a FIFO comprising:
steering/reset logic that generates a read output pulse in said read clock domain on sequential outputs and simultaneously generates a reset pulse on other outputs;
a parallel register that stores said read output pulse and generates a rising edge signal in said read clock domain;
synchronizers connected in parallel to said parallel register that detect said rising edge signal and generate decrement pulses in said write clock domain;
an up/down counter that receives said decrement pulses in parallel and decrements said up/down counter in response to said decrement pulses, and receives a read strobe pulse and increments said up/down counter in response to said read strobe pulse, said up/down counter having a counter output that provides a read count signal;
a register that generates a read counter value in said write clock domain that indicates the amount of data that is present in said FIFO.
10. The device of claim 9 wherein said parallel register comprises a predetermined number of flip-flops that are connected in parallel to said steering/reset logic, said predetermined number being greater than or equal to the number of clock pulses in said read clock domain that are required to clock a read pulse from said steering/reset logic to said up/down counter.