Method to quickly estimate inductance for timing models
View Patent ↗A method of estimating an inductance delay includes determining a resistance-capacitance (RC) delay with resistances and capacitances of a network and estimating an inductance delay of the network by determining a propagation delay of an electromagnetic (EM) field across wires of the network. Additionally, the method includes determining if the RC delay is below a specified threshold and adding the estimated inductance delay to the RC delay to determine a total time to propagate voltage swings through the network if the RC delay is below the specified threshold.
1. A method of estimating an inductance delay comprising:
calculating a resistance-capacitance (RC) delay with resistances and capacitances of a network;
estimating an inductance delay of the network by determining a propagation delay of an electromagnetic (EM) field across wires of the network;
determining if the estimated inductance delay should be added to the RC delay; and
if the determining indicates the estimated inductance delay should be added to the RC delay, adding the estimated inductance delay to the RC delay to determine a total time to propagate voltage swings through the network.
2. The method of claim 1 , wherein the determining the propagation delay of the EM field across the wires of the network comprises:
determining a total wire length of the network; and
dividing the total wire length of the network by the speed of light in a chip dielectric.
3. The method of claim 1 , wherein the determining the propagation delay of the EM field across the wires of the network assumes that the EM field will propagate through the network at the speed of light in a chip dielectric.
4. The method of claim 1 , wherein the RC delay of the network is calculated by building a parasitic model of capacitors and resistors of the network.
5. The method of claim 1 , wherein the total time to propagate voltage swings through the network at 1/e voltage is determined according to the equation
Delay at 1/ e voltage= RC +(length of wire)/ c,
wherein R is resistance, C is capacitance and c is the speed of light in a chip dielectric.
6. The method of claim 1 , wherein the total time to propagate voltage swings through the network at ½ voltage is determined according to the equation
Delay at ½ voltage=0.7×( RC +(length of wire)/ c ),
wherein R is resistance, C is capacitance and c is the speed of light in a chip dielectric.
7. The method of claim 1 , wherein if the determining indicates the estimated inductance delay should not be added to the RC delay, the inductance delay is ignored in determining the total time to propagate voltage swings through the network.
8. The method of claim 1 , wherein the determining if the estimated inductance delay should be added to the RC delay comprises using at least one of an RC delay filter and a wire length filter.
9. A method of estimating an inductance delay comprising:
determining a resistance-capacitance (RC) delay with resistances and capacitances of a network by building a parasitic model of capacitors and resistors of the network;
estimating an inductance delay of the network by determining a propagation delay of an electromagnetic (EM) field across wires of the network by determining a total wire length of the network and dividing the total wire length of the network by the speed of light in a chip dielectric;
determining if the estimated inductance delay should be added to the RC delay; and
if the determining indicates the estimated inductance delay should be added to the RC delay, adding the estimated inductance delay to the RC delay to determine a total time to propagate voltage swings through the network according to one of the equations:
Delay at 1/ e voltage= RC +(length of wire)/ c , and
Delay at ½ voltage=0.7×( RC +(length of wire)/ c ),
wherein R is resistance, C is capacitance and c is the speed of light in the chip dielectric.