I/O connection scheme for QFN leadframe and package structures
View Patent ↗Methods, systems, and apparatuses for integrated circuit packages and lead frames are provided. A quad flat no-lead (QFN) package includes a plurality of peripherally positioned pins, a die-attach paddle, an integrated circuit die, and an encapsulating material. The die-attach paddle is positioned within a periphery formed by the pins. The die is attached to the die-attach paddle. The encapsulating material encapsulates the die on the die-attach paddle, encapsulates bond wires connected between the die and the pins, and fills a space between the pins and the die-attach paddle. One or more of the pins are extended. An extended pin may be elongated, L shaped, T shaped, or “wishbone” shaped. The extended pin(s) enable wire bonding of additional ground, power, and I/O (input/output) pads of the die in a manner that does not significantly increase QFN package cost.
1. A quad flat no-lead (QFN) package, comprising:
a plurality of peripherally positioned pins;
a die-attach paddle positioned within a ring formed by the plurality of peripherally positioned pins;
an integrated circuit die attached to the die-attach paddle; and
an encapsulating material that encapsulates the integrated circuit die on the die-attach paddle and at least a portion of the plurality of peripherally positioned pins;
wherein a first pin of the plurality of peripherally positioned pins has a first portion that extends from a peripheral edge towards the die-attach paddle and a second portion that extends from an end of the first portion to between the die-attach paddle and a second pin of the plurality of peripherally positioned pins; and
wherein the first pin is electrically isolated from the die-attach paddle.
2. The QFN package of claim 1 , wherein the first pin is L-shaped.
3. The QFN package of claim 1 , wherein the first pin further has a third portion that extends from the end of the first portion to between the die-attach paddle and a fifth pin of the a plurality of peripherally positioned pins.
4. The QFN package of claim 3 , wherein the first pin is T-shaped.
5. The QFN package of claim 1 , wherein the first pin further has a third portion that extends from the second portion around a corner of the die-attach paddle.
6. A quad flat no-lead (QFN) package, comprising:
a plurality of peripherally positioned pins;
a die-attach paddle positioned within a ring formed by the plurality of peripherally positioned pins;
an integrated circuit die attached to the die-attach paddle; and
an encapsulating material that encapsulates the integrated circuit die on the die-attach paddle and at least a portion of the plurality of peripherally positioned pins;
wherein a first pin of the plurality of peripherally positioned pins has a first portion that extends from a peripheral edge towards the die-attach paddle and a second portion that extends from an end of the first portion to between the die-attach paddle and a second pin of the plurality of peripherally positioned pins; and
wherein the first pin is coupled to the die-attach paddle.
7. A quad flat no-lead (QFN) package, comprising:
a plurality of peripherally positioned pins;
a die-attach paddle positioned within a ring formed by the plurality of peripherally positioned pins;
an integrated circuit die attached to the die-attach paddle;
a bond wire; and
an encapsulating material that encapsulates the integrated circuit die on the die-attach paddle and at least a portion of the plurality of peripherally positioned pins;
wherein a first pin of the plurality of peripherally positioned pins has a first portion that extends from a peripheral edge towards the die-attach paddle and a second portion that extends from an end of the first portion to between the die-attach paddle and a second pin of the plurality of peripherally positioned pins; and
wherein the bond wire is coupled between a pad of the die and the first pin.
8. A quad flat no-lead (QFN) package, comprising:
a plurality of peripherally positioned pins;
a die-attach paddle positioned within a ring formed by the plurality of peripherally positioned pins;
an integrated circuit die attached to the die-attach paddle; and
an encapsulating material that encapsulates the integrated circuit die on the die-attach paddle and at least a portion of the plurality of peripherally positioned pins;
wherein a first pin of the plurality of peripherally positioned pins has a first portion that extends from a peripheral edge towards the die-attach paddle and a second portion that extends from an end of the first portion to between the die-attach paddle and a second pin of the plurality of peripherally positioned pins; and
wherein a third pin of the plurality of peripherally positioned pins has a first portion that extends from the peripheral edge towards the die-attach paddle and a second portion that extends from an end of the first portion of the third pin to between the die-attach paddle and the second portion of the first pin of the plurality of peripherally positioned pins.
9. A lead frame for an integrated circuit package, comprising:
a ring shaped outer frame;
a plurality of leads extending inwardly from an inner edge of the ring shaped outer frame; and
a die-attach paddle positioned within the ring shaped frame and coupled to the ring shaped frame by at least one interconnect;
wherein a first lead of the plurality of leads has a first portion that extends from the inner edge towards the die-attach paddle and a second portion that extends from an end of the first portion to between the die-attach paddle and a second lead of the plurality of leads; and
wherein the first lead is electrically isolated from the die-attach paddle when separated from the ring shaped outer frame.
10. The lead frame of claim 9 , wherein the first lead is L-shaped.
11. The lead frame of claim 9 , wherein the first lead further has a third portion that extends from the end of the first portion to between the die-attach paddle and a fifth lead of the plurality of leads.
12. The lead frame of claim 11 , wherein the first lead is T-shaped.
13. The lead frame of claim 9 , wherein the first lead further has a third portion that extends from the second portion around a corner of the die-attach paddle.
14. A lead frame for an integrated circuit package, comprising:
a ring shaped outer frame;
a plurality of leads extending inwardly from an inner edge of the ring shaped outer frame; and
a die-attach paddle positioned within the ring shaped frame and coupled to the ring shaped frame by at least one interconnect;
wherein a first lead of the plurality of leads has a first portion that extends from the inner edge towards the die-attach paddle and a second portion that extends from an end of the first portion to between the die-attach paddle and a second lead of the plurality of leads; and
wherein the first lead is coupled to the die-attach paddle.
15. A lead frame for an integrated circuit package, comprising:
a ring shaped outer frame;
a plurality of leads extending inwardly from an inner edge of the ring shaped outer frame; and
a die-attach paddle positioned within the ring shaped frame and coupled to the ring shaped frame by at least one interconnect;
wherein a first lead of the plurality of leads has a first portion that extends from the inner edge towards the die-attach paddle and a second portion that extends from an end of the first portion to between the die-attach paddle and a second lead of the plurality of leads; and
wherein a third lead of the plurality of leads has a first portion that extends from the peripheral edge towards the die-attach paddle and a second portion that extends from an end of the first portion of the third lead to between the die-attach paddle and the second portion of the first lead of the plurality of leads.
16. A quad flat no-lead (QFN) package, comprising:
a plurality of peripherally positioned pins;
a die-attach paddle positioned within a ring formed by the plurality of peripherally positioned pins;
an integrated circuit die attached to the die-attach paddle; and
an encapsulating material that encapsulates the integrated circuit die on the die-attach paddle and at least a portion of the plurality of peripherally positioned pins;
wherein a first pin of the plurality of peripherally positioned pins has a first portion that extends from a peripheral edge towards the die-attach paddle and a second portion that extends from an end of the first portion to between the die-attach paddle and a second pin of the plurality of peripherally positioned pins; and
wherein a third pin of the plurality of peripherally positioned pins has a width along the peripheral edge that is greater than a width of a fourth pin of the plurality of peripherally positioned pins along the peripheral edge.
17. The QFN package of claim 16 , further comprising:
a first plurality of bond wires coupled between the die and the third pin; and
a second plurality of bond wires coupled between the die and the fourth pin;
wherein the first plurality of bond wires includes a greater number of bond wires than the second plurality of bond wires.
18. A lead frame for an integrated circuit package, comprising:
a ring shaped outer frame;
a plurality of leads extending inwardly from an inner edge of the ring shaped outer frame; and
a die-attach paddle positioned within the ring shaped frame and coupled to the ring shaped frame by at least one interconnect;
wherein a first lead of the plurality of leads has a first portion that extends from the inner edge towards the die-attach paddle and a second portion that extends from an end of the first portion to between the die-attach paddle and a second lead of the plurality of leads; and
wherein a third lead of the plurality of leads has a width along the inner edge that is greater than a width of a fourth lead of the plurality of leads along the inner edge.