Comparator and A/D converter
View Patent ↗A comparator used in a parallel-type A/D converter, wherein a comparator 100 includes reset transistors mra and mrb. When the comparator 100 is in the Reset state, the inverted signal /CLK of the clock signal is given to the PMOS reset transistors mra and mrb so as to forcibly reset both of the voltages at two internal nodes Va and Vb being a differential pair to a predetermined reset voltage by the reset transistors mra and mrb. The inverted signal /CLK of the clock signal is produced with a predetermined delay. Thus, when the comparator 100 is in the Reset state, the point in time at which to cancel the reset of the internal nodes Va and Vb is delayed from that at which the comparator performs a comparison operation. Therefore, even if the frequency of the clock signal and the frequency of the analog input signal are high, the voltages at the internal nodes forming a differential pair are well-balanced when the comparator is in the Reset state, thus improving the voltage comparison precision.
1. A comparator for receiving a plurality of differential voltage pairs and performing a comparison operation, in synchronism with a clock signal, on each difference voltage of the plurality of differential voltage pairs, comprising:
an input transistor section for receiving the plurality of differential voltage pairs and performing a predetermined weighting operation and a voltage-current conversion operation on the plurality of differential voltage pairs, thus performing a differential comparison operation on each difference voltage of the plurality of weighted differential voltage pairs, and outputting a differential current pair being a result of the differential comparison;
a positive feedback section for receiving the differential comparison result from the input transistor section and, in synchronism with the clock signal, amplifying the received differential comparison result to a predetermined voltage level to output the amplified result as a comparison result of the comparator, when the clock signal is at a predetermined level; and
a reset section for resetting both of two connecting portions between the input transistor section and the positive feedback section to a predetermined reset voltage when the clock signal is not at the predetermined level, wherein:
the reset section includes a reset voltage generator for generating the predetermined reset voltage;
the reset voltage generator includes a replica circuit including at least one circuit portion of a differential pair of a circuit identical to a circuit formed by the input transistor section and the positive feedback section; and
the reset voltage generator outputs, as the predetermined reset voltage, a voltage at a connecting portion between the input transistor section and the positive feedback section of the replica circuit.
2. The comparator of claim 1 , wherein the predetermined reset voltage used in the reset operation by the reset section is a ground voltage.
3. A comparator for receiving a plurality of differential voltage pairs and performing a comparison operation, in synchronism with a clock signal, on each difference voltage of the plurality of differential voltage pairs, comprising:
an input transistor section for receiving the plurality of differential voltage pairs and performing a predetermined weighting operation and a voltage-current conversion operation on the plurality of differential voltage pairs, thus performing a differential comparison operation on each difference voltage of the plurality of weighted differential voltage pairs, and outputting a differential current pair being a result of the differential comparison;
a positive feedback section including a pair of feedback transistors for receiving the differential comparison result from the input transistor section and, in synchronism with the clock signal, amplifying the received differential comparison result to a predetermined voltage level to output the amplified result as a comparison result of the comparator, when the clock signal is at a predetermined level; and
a pair of switch transistors each being connected in series with one of the pair of feedback transistors of the positive feedback section, wherein the switch transistors are switched by the clock signal to allow or prohibit an operation of the positive feedback section; and
a reset section for resetting both of two connecting portions between the pair of feedback transistors of the positive feedback section and the pair of switch transistors to a predetermined reset voltage when the clock signal is not at the predetermined level, wherein:
the reset section includes a reset voltage generator for generating the predetermined reset voltage;
the reset voltage generator includes a replica circuit including at least one circuit portion of a differential pair of a circuit identical to a circuit formed by the input transistor section, the positive feedback section and the pair of switch transistors; and
the reset voltage generator outputs, as the predetermined reset voltage, a voltage at a connecting portion between the feedback transistor of the positive feedback section and the switch transistor of the replica circuit.
4. The comparator of claim 3 , wherein the predetermined reset voltage used in the reset operation by the reset section is a ground voltage.
5. The comparator of any of claim 1 , 2 , 3 or 4 , wherein:
the reset section is given an inverted signal of the clock signal which is given to the positive feedback section; and
a delay circuit is provided for delaying the inverted signal of the clock signal given to the reset section by a predetermined amount of time.
6. An A/D converter for performing an A/D conversion by using the comparator of any of claim 1 , 2 , 3 , or 4 .
7. An A/D converter for performing an A/D conversion by using the comparator of claim 5 .