IP Library Granted Patent US 7,679,400
Granted Patent B2
US 7,679,400 · App. 12/123,670 · Granted Mar 16, 2010

System and method for local generation of programming data in a programmable device

Assignee: Panasonic Corporation
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Quick Facts
Patent No.
US 7,679,400
App. No.
12/123,670
Granted
Mar 16, 2010
Kind
B2
Abstract

An apparatus for and method of programming a programmable logic device, the programmable logic device comprising a plurality of serially connected programmable logic regions. The method comprises the steps of receiving initial programming data for programming the plurality of serially connected programmable logic regions and receiving transformation data related to the presence and location of at least one faulty serially connected programmable logic region. The method also comprises the steps of generating bypass programming data which, in use, renders a serially connected programmable logic region logically invisible and generating effective programming data by incorporating, using information found in the transformation data, the bypass programming data into the initial programming data. Finally, the method comprises the step of programming the programmable logic device using the effective programming data such that the at least one faulty serially connected programmable logic region is programmed with the bypass programming data.

Claims (30)

1. A method of programming a programmable logic device, the programmable logic device comprising a plurality of serially connected programmable logic regions, the method comprising:

receiving initial programming data for programming the plurality of serially connected programmable logic regions;

receiving transformation data related to the presence and location of at least one faulty serially connected programmable logic region;

generating bypass programming data which, in use, renders a serially connected programmable logic region logically invisible;

generating effective programming data by incorporating, using information found in the transformation data, the bypass programming data into the initial programming data;

programming the programmable logic device using the effective programming data such that the at least one faulty serially connected programmable logic region is programmed with the bypass programming data,

wherein generating the effective programming data comprises:

determining, using the transformation data, a specific point where the bypass programming data should be incorporated into the initial programming data, the specific point being related to the physical location of the faulty serially connected programmable logic region; and

inserting the bypass programming data into the initial programming data at the specific point.

2. The method of claim 1 , wherein inserting the bypass programming data into the initial programming data further comprises:

halting the reception of the initial programming data until the bypass data has been inserted into the initial programming data; and

resuming the reception of the initial programming data.

3. The method of claim 1 , wherein inserting the bypass programming data into the initial programming data further comprises:

storing incoming initial programming data into memory until the bypass data has been inserted into the initial programming data; and

reading the initial programming data which was stored in the memory.

4. An apparatus for programming a programmable logic device, the programmable logic device comprising a plurality of serially connected programmable logic regions, the apparatus comprising:

an initial programming data receiver which receives initial programming data for programming the plurality of serially connected programmable logic regions;

a transformation data receiver which receives transformation data related to the presence and location of at least one faulty serially connected programmable logic region;

a bypass programming data generator which generates bypass programming data which, in use, renders a serially connected programmable logic region logically invisible;

an effective programming data generator which generates effective programming data by incorporating, using information found in the transformation data, the bypass programming data into the initial programming data;

a programmer which programs the programmable logic device using the effective programming data such that the at least one faulty serially connected programmable logic region is programmed with the bypass programming data,

wherein the effective programming data generator comprises:

a determiner which determines, using the transformation data, a specific point where the bypass programming data should be incorporated into the initial programming data, the specific point being related to the physical location of the faulty serially connected programmable logic region; and

an inserter which inserts the bypass programming data into the initial programming data at the specific point.

5. The apparatus of claim 4 , wherein the inserter comprises:

a halter which halts the reception of the initial programming data until the bypass data has been inserted into the initial programming data; and

a resumer which resumes resume the reception of the initial programming data.

6. The apparatus of claim 4 , wherein the inserter comprises:

a storer which stores the incoming initial programming data into memory until the bypass data has been inserted into the initial programming data; and

a reader which reads the initial programming data which was stored in the memory.

Assignments (2)
CHANGE OF NAME Recorded Nov 21, 2008
From: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
To: PANASONIC CORPORATION
Reel/Frame 021897/0606 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2008
From: DEELEY, SIMON
To: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Reel/Frame 021330/0637 →
Priority Claims (1)
EP 07108690 · May 22, 2007 · regional
Continuity (1)
Related Publication 20080290895A1 · Nov 27, 2008