Semiconductor circuit and switching power supply apparatus

1. A power supply apparatus, comprising:

a first switching regulator receiving an input voltage and forming a first voltage; and

a second switching regulator receiving the first voltage and forming a second voltage,

wherein the second switching regulator includes an N-phase (N is two or more) switching regulator that has N output circuits;

wherein the first voltage is set to be N times a target value of the second voltage; and

wherein the input voltage is set to be higher than the first voltage.

2. The power supply apparatus according to claim 1 ,

wherein the first switching regulator is a single-phase switching regulator operated by a first PWM pulse.

3. The power supply apparatus according to claim 2 ,

wherein the second switching regulator includes:

the N output circuits;

N inductors each having one-end thereof coupled to an output terminal of each of the N output circuits; and

a capacitor being coupled in common to the other ends of the N inductors and forming the second voltage; and

wherein the N output circuits are supplied with N-phase second PWM pulses each having a phase difference corresponding to 360 degrees/N.

4. The power supply apparatus according to claim 3 ,

wherein the N-phase second PWM pulses are formed by an N-phase PWM modulator receiving a triangular wave or clock signal.

5. The power supply apparatus according to claim 4 ,

wherein a frequency of the first PWM pulse is set to be lower than that of the second PWM pulses.

6. The power supply apparatus according to claim 5 , further comprising a VID decoder:

wherein the first voltage is set according to a first control signal of the VID decoder; and

wherein the second voltage is set according to a second control signal of the VID decoder.

7. The power supply apparatus according to claim 6 :

wherein a first reference voltage supplied to a first error amplifier composing the first switching regulator is controlled by the first control signal of the VID decoder to set the first voltage; and

wherein a second reference voltage supplied to a second error amplifier composing the second switching regulator is controlled by the second control signal of the VID decoder to set the second voltage.

8. The power supply apparatus according to claim 6 :

wherein the first switching regulator forms the first voltage according to an output signal of a first error amplifier that receives a first reference voltage and a first divided voltage of the first voltage, the first divided voltage being controlled by the first control signal of the VID decoder to set the first voltage; and

wherein the second switching regulator forms the second voltage according to an output signal of a second error amplifier that receives a second reference voltage and a second divided voltage of the second voltage, the second divided voltage being controlled by the second control signal of the VID decoder to set the second voltage.

9. The power supply apparatus according to claim 5 :

wherein the first switching regulator includes a first semiconductor device that has a first drive circuit receiving the first PWM pulse and an output MOSFET circuit driven thereby in one package;

wherein the second switching regulator includes N-phase second semiconductor devices that have N drive circuits receiving the second PWM pulses having N phases, respectively, and N output MOSFET circuits driven thereby, respectively, in one package; and

wherein the power supply apparatus further comprises

a third semiconductor device that is provided in common to the first semiconductor device and the N second semiconductor devices and forms the first PWM pulse and the second PWM pulses having N phases.

10. The power supply apparatus according to claim 9 ,

wherein the third semiconductor device further includes a VID decoder;

wherein the first voltage is set according to a first control signal of the VID decoder; and

wherein the second voltage is set according to a second control signal of the VID decoder.

11. The power supply apparatus according to claim 10 ,

wherein each of the first and second semiconductor devices includes a first, a second, and a third semiconductor chips;

wherein the first semiconductor chip forms the drive circuit;

wherein the second semiconductor chip forms one output MOSFET of the output MOSFET circuit and is a first power MOSFET that has a vertical MOS structure in which current flows in a vertical direction of the semiconductor chip; and

wherein the third semiconductor chip forms the other output MOSFET of the output MOSFET circuit and is a second power MOSFET that has a vertical MOS structure in which current flows in a vertical direction of the semiconductor chip.