IP Library › Granted Patent US 7,951,634
Granted Patent B2
US 7,951,634 · App. 12/173,739 · Granted May 31, 2011

Method and device for protecting interferometric modulators from electrostatic discharge

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,951,634
App. No.
12/173,739
Granted
May 31, 2011
Kind
B2
Abstract

A MEMS device such as an interferometric modulator includes an integrated ESD protection element capable of shunting to ground an excess current carried by an electrical conductor in the MEMS device. The protection element may be a diode and may be formed by depositing a plurality of doped semiconductor layers over the substrate on which the MEMS device is formed.

Claims (19)

1. A method of making an interferometric modulator device, the method comprising:

depositing a first electrode layer over a substrate;

depositing a sacrificial layer over the first electrode layer;

depositing a second electrode layer over the sacrificial layer;

depositing a plurality of doped semiconductor layers over the substrate; and

forming a ground plane over the substrate, the ground plane and the plurality of doped semiconductor layers being configured to shunt to ground an excess current carried by at least one of the first electrode layer and the second electrode layer.

2. The method of claim 1 , further comprising removing the sacrificial layer.

3. The method of claim 1 , further comprising depositing the ground plane over the plurality of doped semiconductor layers.

4. The method of claim 1 , further comprising depositing the plurality of doped semiconductor layers over the ground plane.

5. The method of claim 1 , further comprising depositing the ground plane near a periphery of the substrate.

6. The method of claim 1 , wherein the plurality of doped semiconductor layers are deposited at substantially the same level as the first electrode layer.

7. The method of claim 1 , wherein the plurality of doped semiconductor layers are deposited at substantially the same level as the second electrode layer.

8. The method of claim 1 , wherein the plurality of doped semiconductor layers comprises a diode.

9. The method of claim 8 , wherein the diode is selected from the group consisting of a back-to-back Zener diode, a standard Zener diode, a low capacitance Zener diode, a symmetrical Zener diode, and a low capacitance symmetrical diode.

10. The method of claim 9 , wherein the diode is a back-to-back Zener diode.

11. The method of claim 9 , wherein the diode is a standard Zener diode.

12. The method of claim 9 , wherein the diode is a low capacitance Zener diode.

13. The method of claim 9 , wherein the diode is a symmetrical Zener diode.

14. The method of claim 9 , wherein the diode is a low capacitance symmetrical diode.