Reference voltage generating circuit and constant voltage circuit
View Patent ↗A reference voltage generating circuit for producing a predetermined reference voltage at an output node includes a depletion-type n-channel field-effect transistor serving as a first field-effect transistor having one node thereof coupled to a power supply voltage, a second field-effect transistor having one node thereof coupled to another node of the first field-effect transistor and having a highly-doped n-type gate, and a third field-effect transistor having one node thereof coupled to another node of the second field-effect transistor, another node thereof coupled to a ground voltage, and a highly-doped p-type gate.
1. A reference voltage generating circuit for producing a predetermined reference voltage at an output node, comprising:
a depletion-type n-channel field-effect transistor serving as a first field-effect transistor having one node thereof coupled to a power supply voltage;
a second field-effect transistor having one node thereof coupled to another node of the first field-effect transistor and having a highly-doped n-type gate; and
a third field-effect transistor having one node thereof coupled to another node of the second field-effect transistor, another node thereof coupled to a ground voltage, and a highly-doped p-type gate,
wherein a gate of the first field-effect transistor is coupled to a joint point between the first field-effect transistor and the second field-effect transistor, substrate gates of the first through third field-effect transistors coupled to the ground voltage, and the gate of each of the second and third field-effect transistors coupled to a joint point serving as the output node between the second field-effect transistor and the third field-effect transistor, and wherein each of the second and third field-effect transistors is configured to have such a ratio of a channel width to a channel length that a characteristic indicating a relationship between a gate-source voltage and a drain current exhibit a positive temperature dependency for both of the second and third field effect transistors or a negative temperature dependency for both of the second and third field-effect transistors,
and wherein a channel of the second field-effect transistor having the highly-doped n-type gate has impurity density equal to an impurity of the third field-effect transistor having the highly-doped p-type gate.
2. The reference voltage generating circuit as claimed in claim 1 , wherein the second field-effect transistor has a ratio S 2 of the channel width to the channel length, and the third field-effect transistor has a ratio S 3 of the channel width to the channel length, S 3 being smaller than S 2 .
3. The reference voltage generating circuit as claimed in claim 2 , wherein each of the second and third field-effect transistors is configured such that S 3 /S 2 is between 0.35 and 0.45.
4. The reference voltage generating circuit as claimed in claim 3 , wherein each of the second and third field-effect transistors is configured such that S 3 /S 2 is between 0.37 and 0.41.
5. A constant voltage circuit for generating a predetermined constant voltage from an input voltage by using a predetermined reference voltage generated by a reference voltage generating circuit as a reference, wherein the reference voltage generating circuit includes:
a depletion-type n-channel field-effect transistor serving as a first field-effect transistor having one node thereof coupled to a power supply voltage;
a second field-effect transistor having one node thereof coupled to another node of the first field-effect transistor and having a highly-doped n-type gate; and
a third field-effect transistor having one node thereof coupled to another node of the second field-effect transistor, another node thereof coupled to a ground voltage, and a highly-doped p-type gate,
wherein a gate of the first field-effect transistor is coupled to a joint point between the first field-effect transistor and the second field-effect transistor, substrate gates of the first through third field-effect transistors coupled to the ground voltage, and the gate of each of the second and third field-effect transistors coupled to a joint point serving to provide the reference voltage between the second field-effect transistor and the third field-effect transistor, and wherein each of the second and third field-effect transistors is configured to have such a ratio of a channel width to a channel length that a characteristic indicating a relationship between a gate-source voltage and a drain current exhibit a positive temperature dependency for both of the second and third field-effect transistors or a negative temperature dependency for both of the second and third field-effect transistors,
and wherein a channel of the second field-effect transistor having the highly-doped n-type gate has impurity density equal to an impurity density of a channel of the third field-effect transistor having the highly-doped p-type gate.
6. The constant voltage circuit as claimed in claim 5 , wherein the second field-effect transistor has a ratio S 2 of the channel width to the channel length, and the third field-effect transistor has a ratio S 3 of the channel width to the channel length, S 3 being smaller than S 2 .
7. The constant voltage circuit as claimed in claim 6 ,wherein each of the second and third field-effect transistors is configured such that S 3 /S 2 is between 0.35 and 0.45.
8. The constant voltage circuit as claimed in claim 7 ,wherein each of the second and third field-effect transistors is configured such that S 3 /S 2 is between 0.37 and 0.41.