NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE
A non-volatile semiconductor memory device is provided. A gate electrode configuring a memory cell is turned into floating state and a potential of a gate electrode adjacent thereto is changed, and reduce the potential of the gate electrode by this change of potential and the capacitive coupling. Furthermore, charge sharing is carried out by connecting two gate electrodes, and the voltage of the gate electrode is reduced by capacitive coupling with another gate electrode adjacent thereto, to largely reduce the potential of the gate electrode. Thereby, the voltage level generated by the charge pump circuit can be reduced. As a result, the size of the charge pump circuit can be reduced, or the circuit itself can be eliminated, resulting in reduction of the chip area.
1 . A non-volatile semiconductor memory device comprising:
a semiconductor substrate;
a first charge accumulation film formed on the semiconductor substrate;
a first gate electrode formed on the first charge accumulation film;
a second gate electrode formed adjacent to the first gate electrode; and
a control circuit to control the potential of the first and second gate electrodes, wherein,
at the time of data erase operation which corresponds to the amount of charges accumulated in the first charge accumulation film,
the control circuit operates to supply a first potential to the first gate electrode and a second potential to the second gate electrode respectively,
thereafter, the control circuit operates to turn the first gate electrode into floating state, and,
thereafter, the control circuit operates to supply a fourth potential lower than the second potential to the second gate electrode so as to make the first gate electrode have a third potential lower than the first potential.
2 . The non-volatile semiconductor memory device according to claim 1 further comprising:
a pair of semiconductor regions which are used as a source and a drain of a first transistor containing the first gate electrode in the semiconductor substrate, wherein
the second gate electrode is adjacent to the side of the first gate electrode via a dielectric, and disposed between the pair of the semiconductor regions on the semiconductor substrate.
3 . The non-volatile semiconductor memory device according to claim 1 further comprising:
a second charge accumulation film formed on the semiconductor substrate;
a third gate electrode formed on the second charge accumulation film; and,
a fourth gate electrode formed adjacent to the third gate electrode, wherein
the operation by the control circuit to supply the first potential to the first gate electrode comprises,
an operation of the control circuit to supply a fifth potential to the third gate electrode and a sixth potential to the fourth gate electrode respectively,
thereafter, an operation of the control circuit to turn the third gate electrode into floating state,
thereafter, an operation of the control circuit to supply an eighth potential lower than the sixth potential to the fourth gate electrode so as to make the third gate electrode have a seventh negative potential lower than the fifth potential, and,
thereafter, the control circuit and the first and third gate electrodes are electrically connected by the operation of the control circuit.
4 . The non-volatile semiconductor memory device according to claim 2 further comprising:
a second charge accumulation film formed on the semiconductor substrate;
a third gate electrode formed on the second charge accumulation film; and,
a fourth gate electrode formed adjacent to the third gate electrode, wherein
the operation by the control circuit to supply the first potential to the first gate electrode comprises,
an operation of the control circuit to supply a fifth potential to the third gate electrode and a sixth potential to the fourth gate electrode respectively,
thereafter, an operation of the control circuit to turn the third gate electrode into floating state,
thereafter, an operation of the control circuit to supply an eighth potential lower than the sixth potential to the fourth gate electrode so as to make the third gate electrode have a seventh negative potential lower than the fifth potential, and,
thereafter, the control circuit and the first and third gate electrodes are electrically connected by the operation of the control circuit.
5 . The non-volatile semiconductor memory device according to claim 1 , wherein
the first and second gate electrodes are provided in a memory cell array region, and
no circuit for generating negative voltage is provided outside of the memory cell array region.
6 . The non-volatile semiconductor memory device according to claim 3 , wherein
the first to fourth gate electrodes are provided in the memory cell array region, and
no circuit for generating negative voltage is provided outside of the memory cell array region.
7 . The non-volatile semiconductor memory device according to claim 2 further comprising:
a third charge accumulation film formed on the semiconductor substrate;
a fifth gate electrode formed on the third charge accumulation film; and
a sixth gate electrode formed adjacent to the fifth gate electrode, wherein
after the first gate electrode has a third potential, the control circuit operates to electrically connect the first and the fifth gate electrodes to make the fifth gate electrode have a ninth potential,
thereafter, the control circuit operates to turn the fifth gate electrode into floating state, and
thereafter, the control circuit operates to reduce the potential of the sixth gate electrode to make the fifth gate electrode have a negative tenth potential lower than the ninth potential.
8 . The non-volatile semiconductor memory device according to claim 1 further comprising:
a fourth charge accumulation film formed on the semiconductor substrate;
a seventh gate electrode formed on the fourth charge accumulation film; and
a pair of semiconductor regions to be a source and a drain of a first transistor containing the first gate electrode in the semiconductor substrate, wherein
the second gate electrode is disposed on the side of the first gate electrode via a dielectric,
the seventh gate electrode is disposed on the side of the second gate electrode via a dielectric,
the second and seventh gate electrodes are disposed between the pair of the semiconductor regions on the semiconductor substrate, and
the second potential of the second gate electrode is a potential boosted by boosting the potential of the seventh gate electrode.
9 . The non-volatile semiconductor memory device according to claim 1 , wherein
the first and second gate electrodes are gate electrodes which are included in different memory cells and constitute different word lines, and those word lines are adjacent word lines to each other.
10 . The non-volatile semiconductor memory device according to claim 1 , wherein
the first charge accumulation film is a nitride silicon film.
11 . A non-volatile semiconductor memory device comprising:
a semiconductor substrate;
a first charge accumulation film formed on the semiconductor substrate;
a first gate electrode formed on the first charge accumulation film;
a second gate electrode formed adjacent to the first gate electrode;
a second charge accumulation film formed on the semiconductor substrate;
a third gate electrode formed on the second charge accumulation film;
a fourth gate electrode formed adjacent to the third gate electrode; and
a control circuit to control the potential of the first, second, third and fourth electrodes, wherein
at rewrite operation of the data corresponding to the charges accumulated in the second charge accumulation film,
the control circuit operates to supply a first potential to the first gate electrode, a second potential to the second gate electrode, a third potential to the third date electrode and a fourth potential to the fourth gate electrode respectively,
the control circuit operates to turn the first and third gate electrodes into floating state,
the control circuit operates to supply a sixth potential to the second gate electrode to make the first gate electrode have a fifth potential,
thereafter, the control circuit operates to electrically connect the first and third gate electrodes to make the first and third gate electrodes have a seventh potential which is an intermediate potential between the third and sixth potentials,
thereafter, the control circuit operates to electrically disconnect the third and first gate electrodes to turn the first and third gate electrodes into floating state,
thereafter, the control circuit operates to supply a ninth potential to the fourth gate electrode to make the third gate electrode have an eighth potential,
the ninth potential is higher than the fourth potential when the sixth potential is higher than the second potential, and,
the ninth potential is lower than the fourth potential when the sixth potential is lower than the second potential.
12 . The non-volatile semiconductor memory device according to claim 11 , further comprising:
a third charge accumulation film formed on the semiconductor substrate;
a fifth gate electrode formed on the third charge accumulation film; and
a sixth gate electrode formed adjacent to the fifth gate electrode, wherein
the control circuit operates to electrically connect the third and fifth gate electrodes to make the fifth gate electrode have a tenth potential,
thereafter, the control circuit operates to electrically disconnect the third and fifth gate electrodes to turn the third and fifth gate electrodes into floating state, and
the control circuit operates to supply a twelfth potential to the sixth gate electrode to make the fifth gate electrode have an eleventh potential.
13 . The non-volatile semiconductor memory device according to claim 12 , wherein
the first to sixth gate electrodes are provided in one memory mat,
the memory mat includes a plurality of fourth charge accumulation films except the first to third charge accumulation films, a plurality of seventh gate electrodes respectively formed on the plurality of fourth charge accumulation films, and a plurality of eighth gate electrodes formed adjacent to the seventh gate electrodes, and
the control circuit repeats an operation to electrically connect/disconnect the plurality of seventh gate electrodes and other seventh gate electrodes, and an operation to change the potential of the eighth gate electrodes adjacent to the seventh gate electrodes to change the potential of the seventh gate electrodes, on the plurality of seventh and eighth gate electrodes in the memory mat, to make the data corresponding to the volume of the charges accumulated in the first to fourth charge accumulation films become to same data.
14 . The non-volatile semiconductor memory device according to claim 12 , wherein
the first and second gate electrodes are included in one memory cell,
the third and fourth gate electrodes are included in one memory cell, and
the fifth and sixth gate electrodes are included in one memory cell.
15 . The non-volatile semiconductor memory device according to claim 14 , wherein
the first and second gate electrodes constitute a split gate type memory cell,
the third and fourth gate electrodes constitute a split gate type memory cell,
the fifth and sixth gate electrode constitute a split gate type memory cell, and,
the first to third charge accumulation films are nitride silicon films.
16 . The non-volatile semiconductor memory device according to claim 15 , wherein
the rewrite operation is an erase operation,
the first to sixth gate electrodes are provided in a memory cell array region, and
no circuit for generating negative voltage is provided outside of the memory cell array region.
17 . A non-volatile semiconductor memory device comprising:
a semiconductor substrate;
a first charge accumulation film formed on the semiconductor substrate;
a first gate electrode formed on the first charge accumulation film;
a second gate electrode formed adjacent to the first gate electrode;
a second charge accumulation film formed on the semiconductor substrate;
a third gate electrode formed on the second charge accumulation film;
a fourth gate electrode formed adjacent to the third gate electrode;
a first switch to turn the first gate electrode into floating state; and
a second switch to turn the second gate electrode into floating state.
18 . A non-volatile semiconductor memory device according to claim 17 further comprising:
a third switch to electrically connect the first and third gate electrodes.
19 . (canceled)
20 . (canceled)