IP Library Granted Patent US 7,709,921
Granted Patent B2
US 7,709,921 · App. 12/199,558 · Granted May 4, 2010

Photodiode and photodiode array with improved performance characteristics

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Quick Facts
Patent No.
US 7,709,921
App. No.
12/199,558
Granted
May 4, 2010
Kind
B2
Abstract

The present invention is a photodiode and/or photodiode array, having a p+ diffused area that is smaller than the area of a mounted scintillator crystal, designed and manufactured with improved device characteristics, and more particularly, has relatively low dark current, low capacitance and improved signal-to-noise ratio characteristics. More specifically, the present invention is a photodiode and/or photodiode array that includes a metal shield for reflecting light back into a scintillator crystal, thus allowing for a relatively small p+ diffused area.

Claims (33)

1. A photodiode comprising:

a low resistivity substrate having at least a front side and a back side, wherein said low resistivity is in the range of 1000 ohm cm to 2000 ohm cm;

a shallow p+ diffused region on said front side, wherein said shallow p+ region is smaller than a scintillator crystal mounted on the front side of the photodiode;

at least one back side cathode contact and at least one front side anode contact, comprised of metal; and

a reflective metal shield on at least a portion of said front side, wherein said metal shield reflects incident light back into said scintillator crystal.

2. The photodiode of claim 1 wherein said scintillator crystal mounted on the front side of the photodiode has a top surface area of 2 mm×2 mm.

3. The photodiode of claim 1 wherein the shallow p+ diffused region is on the order of 1 mm or less in length and 1 mm or less in width.

4. The photodiode of claim 1 wherein the reflective metal shield comprises aluminum.

5. The photodiode of claim 1 , wherein a distance between the shallow p+ diffused region and an edge of the photodiode ranges from 0.3 mm to 0.5 mm.

6. The photodiode of claim 1 further comprising an anti-reflective layer formed from SiO 2 having a thickness of 900 Å.

7. The photodiode of claim 1 further comprising an anti-reflective layer formed from SiO 2 having a thickness of 150 Å and Si 3 N 4 having a thickness of 400 Å, for a total layer thickness of 550 Å.

8. A photodiode array comprising:

a low resistivity substrate having at least a front side and a back side, wherein said low resistivity is in the range of 1000 ohm cm to 2000 ohm cm;

a plurality of diode elements integrally formed in the substrate forming said array, wherein each diode element has a shallow p+ diffused region on said front side, wherein said shallow p+ region is smaller than a scintillator crystal mounted on the front side of the photodiode;

at least one back side cathode contact and at least one front side anode contact, comprised of metal; and

a reflective metal shield on at least a portion of said front side, wherein said metal shield reflects incident light back into the scintillator crystal.

9. The photodiode array of claim 8 wherein said scintillator crystal mounted on the front side of the photodiode element has a top surface area of 2 mm×2 mm.

10. The photodiode array of claim 8 wherein the shallow p+ diffused region is approximately 1 mm or less in length and 1 mm or less in width.

11. A method of fabricating a photodiode on a low resistivity substrate wafer having a front side and a back side, said method comprising the steps of:

providing an oxide layer on both the front side and the back side;

implementing an etching process on both the front side and back side to define a plurality of regions on the front side and back side;

filling the plurality of regions with n+ dopant;

depositing an oxide layer on both the front side and the back side of the wafer;

creating a deep p+ diffused region on the front side;

fabricating an active area on said front side, wherein said active area is smaller than a scintillator crystal mounted on the front side of the photodiode;

forming an anti-reflective layer on the front side of said device;

forming a shallow p+ active area region;

forming at least one contact window; and

performing a metal deposition process to etch metal on both the front side and back side of the device wafer, wherein said metal deposition process creates connections and wherein said metal deposition process forms a reflective metal shield on the front side.

12. The method of claim 11 wherein said low resistivity substrate has a resistivity in the range of 1000 ohm cm to 2000 ohm cm.

13. The method of claim 11 wherein the step of providing an oxide layer on both the front side and the back side results in an oxide layer having a thickness of approximately 10,000 Å.

14. The method of claim 11 wherein said anti-reflective layer is formed on said front side of said device via thermal growth of a layer of SiO 2 , having a thickness of 150 Å followed by LPCVD deposition of Si 3 N 4 , having a thickness of 400 Å, for a total layer thickness of 550 Å.

15. The method of claim 12 wherein the metal shield on the front side of the device wafer reflects incident light back into the scintillator crystal mounted on the photodiode.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Jul 1, 2025
From: WELLS FARGO BANK, NATIONAL ASSOCIATION
To: OSI OPTOELECTRONICS, INC.
Reel/Frame 071581/0725 →
NUNC PRO TUNC ASSIGNMENT Recorded Feb 22, 2011
From: BUI, PETER STEVEN; TANEJA, NARAYAN DASS
To: OSI OPTOELECTRONICS, INC.
Reel/Frame 025845/0992 →
NOTICE OF GRANT OF SECURITY INTEREST IN PATENTS Recorded Oct 19, 2010
From: OSI OPTOELECTRONICS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 025150/0964 →