Wafer processing apparatus having a tunable electrical resistivity
View Patent ↗An article with an etch resistant coating is disclosed. The article is a heating element, wafer carrier, or electrostatic chuck. The article has a base substrate made of a ceramic or other material, and further has one or more electrodes for resistance heating or electromagnetic chucking or both. The eth resistant coating has a plurality of regions made from materials having different electrical volume resistivities, such that the overall coating has a bulk resistivity that can be tailored by varying the relative size of each region.
1. A wafer carrier comprising a body, said body comprising a substrate and an electrode element, the wafer carrier further comprising an outer coating disposed on at least a portion of an outer surface of said body, said outer coating comprising dielectric material and having at least two regions of different electrical resistivity, wherein a first region adjacent said electrode comprises aluminum nitride of higher density relative to at least one other region, and a second region comprises aluminum nitride of lower density relative to at least said first region.
2. A wafer carrier according to claim 1 , wherein the outer coating is about 25 to 500 micrometers thick.
3. A wafer carrier according to claim 1 , wherein the relative sizes of the regions are selected to provide a desired bulk electrical resistivity to the outer coating within the Johnson-Rahbeck regime at a desired temperature of from 150 to 600° C.
4. A wafer carrier according to claim 1 , wherein said regions comprise one or more layers through a thickness of the coating.
5. A wafer carrier according to claim 4 , wherein a said layer adjacent said electrode comprises aluminum nitride and another layer comprises aluminum oxynitride.
6. A wafer carrier according to claim 1 , wherein said first region adjacent said electrode has at least 25% lower electrical resistivity as compared to the bulk resistivity of the outer coating, and at least another region has at least 25% higher electrical resistivity as compared to the bulk resistivity of the outer coating.
7. A wafer carrier according to claim 1 , wherein said first region adjacent said electrode comprises aluminum nitride comprising less than 0.6 wt % oxygen, and at least another region comprises aluminum nitride comprising greater than 0.6 wt % oxygen.
8. A wafer carrier according to claim 1 , wherein said first region adjacent said electrode comprises AlN having a 25° C. electrical resistivity between 10 3 and 10 14 ohm-cm, and at least one other region has a 25° C. electrical resistivity greater than the first region and between 10 9 and 10 15 ohm-cm.
9. A wafer carrier according to claim 1 , wherein said first region adjacent said electrode comprises AlN having a 600° C. electrical resistivity less than 10 10 ohm-cm, and at least one other region has a 600° C. electrical resistivity of greater than 10 6 ohm-cm.
10. A wafer carrier according to claim 1 , wherein said electrode comprises pyrolytic graphite.
11. A wafer carrier according to claim 10 , wherein said pyrolytic graphite electrode comprises a resistive heating element.
12. A wafer carrier according to claim 1 , wherein said substrate comprises an electrically conductive material.
13. A wafer carrier according to claim 12 , wherein said substrate comprises graphite.
14. A wafer carrier according to claim 12 , further compromising a non-conductive layer positioned between said substrate and said electrode.
15. A wafer carrier according to claim 14 , wherein said non-conductive layer comprises pyrolytic boron nitride.
16. A wafer carrier according to claim 1 , wherein said substrate comprises pyrolytic boron nitride or AlN.
17. A wafer carrier according to claim 1 , wherein said wafer carrier comprises first and second pyrolytic graphite elements, wherein said substrate is disposed between the two pyrolytic graphite elements.
18. A wafer carrier according to claim 17 , wherein the first pyrolytic graphite element is a resistance heating element, and the second pyrolytic graphite element is a chucking electrode.
19. A wafer carrier according to claim 1 , wherein said wafer carrier comprises an electrostatic chuck comprising a body, a chuck electrode deposited on said body, and an outer coating deposited over said chuck electrode, said outer coating comprising a plurality of layers having different resistivities, said outer coating comprising an outer layer comprising AlN.
20. A wafer carrier according to claim 1 , wherein said regions comprise AlN, wherein AlN in a first region differs from AlN in a second region by at least one of: different density, different Al to N stoichiometry, different crystal orientation, crystal structure or crystal size, or the presence and amount of dopants in the AlN.
21. A method of forming a wafer carrier, said method comprising the steps of a) providing a base substrate, b) positioning an electrode on said base substrate, c) depositing a outer coating over said base substrate and electrode, wherein said step c) comprises depositing a plurality of regions comprising materials having different volume resistivities, wherein the overall bulk resistivity of said outer coating at a given temperature can be controlled by modifying the relative amount of each of said materials deposited.
22. A wafer carrier comprising a body, said body comprising a substrate and an electrode element, the wafer carrier further comprising an outer coating disposed on at least a portion of an outer surface of said body, said outer coating comprising dielectric material and having at least two regions of different electrical resistivity, wherein the relative sizes of the regions are selected to provide a desired bulk electrical resistivity to the outer coating within the Johnson-Rahbeck regime at a desired temperature of from 150 to 600° C.