Integrated circuit including doped semiconductor line having conductive cladding

1. An integrated circuit comprising:

an array of memory cells, each memory cell comprising a diode;

a doped semiconductor line formed in a semiconductor substrate, the doped semiconductor line coupled to a row of diodes; and

conductive cladding contacting the doped semiconductor line.

2. The integrated circuit of claim 1 , wherein the doped semiconductor line comprises doped silicon.

3. The integrated circuit of claim 1 , wherein the conductive cladding contacts a first sidewall and a second sidewall of the doped semiconductor line.

4. The integrated circuit of claim 1 , wherein the conductive cladding comprises one of C, TiN, a silicide, and a gas immersion laser doped material.

5. The integrated circuit of claim 1 , further comprising:

spacers contacting a first sidewall and a second sidewall of each diode in the row,

wherein the conductive cladding contacts the spacers.

6. The integrated circuit of claim 5 , wherein the conductive cladding contacts sidewalls of the spacers.

7. The integrated circuit of claim 1 , wherein each memory cell comprises a resistivity changing material coupled to the diode.

8. The integrated circuit of claim 7 , wherein the resistivity changing material comprises one of phase change material and magnetic material.

9. The integrated circuit of claim 1 , wherein each memory cell comprises a vertical diode.

10. A method for fabricating the integrated circuit of claim 1 , the method comprising:

providing the semiconductor substrate including a doped region;

fabricating lines of doped semiconductor material from the doped region of the semiconductor substrate;

fabricating isolation regions between the lines of doped semiconductor material;

fabricating conductive cladding on a first sidewall and a second sidewall of each of the lines of doped semiconductor material; and

fabricating a plurality of diodes coupled to each of the lines of doped semiconductor material.

11. The method of claim 10 , wherein fabricating the conductive cladding comprises fabricating conductive cladding comprising one of C, TiN, a silicide, and a gas immersion laser doped material.

12. The method of claim 10 , wherein fabricating the plurality of diodes comprises:

depositing a first doped semiconductor material layer having a first polarity over the lines of doped semiconductor material;

depositing a second doped semiconductor material layer having a second polarity opposite the first polarity over the first doped semiconductor material layer; and

etching first and second doped semiconductor material layers to provide the plurality of diodes.

13. The method of claim 10 , wherein fabricating the plurality of diodes comprises fabricating a plurality of vertical diodes.

14. The method of claim 10 , wherein fabricating the plurality of diodes comprises:

depositing a dielectric material layer over the lines of doped semiconductor material, the isolation regions, and the conductive cladding;

etching the dielectric material layer to provide openings exposing portions of each line of doped semiconductor material; and

fabricating a diode within each opening.

15. The method of claim 14 , wherein fabricating a diode within each opening comprises:

depositing a semiconductor material into each opening; and

doping the semiconductor material within each opening to provide a diode within each opening.

16. The method of claim 14 , wherein fabricating a diode within each opening comprises:

depositing a first doped semiconductor material having a first polarity into each opening; and

depositing a second doped semiconductor material having a second polarity opposite the first polarity into each opening over the first doped semiconductor material.

17. A method for fabricating the integrated circuit of claim 1 , the method comprising:

providing the semiconductor substrate including a heavily doped first layer having a first polarity, a lightly doped second layer having the first polarity, and a doped third layer having a second polarity opposite the first polarity, the second layer over the first layer and the third layer over the second layer;

etching the first, second, and third layers to provide first, second, and third lines of doped semiconductor material, respectively;

fabricating isolation regions between the first lines of doped semiconductor material;

fabricating conductive cladding on a first sidewall and a second sidewall of each first line of doped semiconductor material; and

etching the second and third lines of doped semiconductor material to provide a plurality of diodes contacting the first lines of doped semiconductor material.

18. The method of claim 17 , wherein fabricating the conductive cladding comprises:

depositing a dielectric material layer over the first, second, and third lines of doped semiconductor material and the isolation regions;

etching the dielectric material layer to expose the isolation regions;

etching the isolation regions to expose the substrate;

selectively etching the substrate and the first lines of doped semiconductor material to provide openings; and

depositing cladding material into the openings to provide the conductive cladding.

19. The method of claim 17 , wherein fabricating the conductive cladding comprises:

forming isolating spacers on sidewalls of the second and third lines of doped semiconductor material;

forming sacrificial spacers on sidewalls of the isolating spacers;

etching the sacrificial spacers and underlying portions of the first lines of doped semiconductor material to provide openings; and

depositing cladding material into the openings to provide the conductive cladding.

20. The method of claim 17 , wherein fabricating the conductive cladding comprises:

depositing cladding material on sidewalls of the first, second, and third lines of doped semiconductor material; and

removing the cladding material from the sidewalls of the second and third lines of doped semiconductor material to provide the conductive cladding.

21. The method of claim 17 , wherein fabricating the conductive cladding comprises:

forming isolating spacers on sidewalls of the first and second lines of doped seimconductor material;

etching the first layer to provide the first lines of doped semiconductor material and to expose sidewalls of the first lines of doped semiconductor material; and

gas immersion laser doping the exposed sidewalls of the first lines doped semiconductor material to provide the conductive cladding.

22. The method of claim 17 , wherein fabricating the conductive cladding comprises:

fabricating conductive cladding comprising one of C, TiN, a silicide, and a gas immersion laser doped material.

23. A system comprising:

a host; and

a memory device communicatively coupled to the host, the memory device comprising:

an array of memory cells, each memory cell comprising a diode coupled to a resistivity changing memory element;

a doped semiconductor line formed in a semiconductor substrate, the doped semiconductor line coupled to a row of diodes; and

conductive cladding contacting the doped semiconductor line.

24. The system of claim 23 , wherein the doped semiconductor line comprises a word line.

25. The system of claim 23 , wherein the memory device further comprises:

a write circuit configured to program each memory cell;

a sense circuit configured to read each memory cell; and

a controller configured to control the write circuit and the sense circuit.