Packet processing on a multi-core processor
View Patent ↗A method for packet processing on a multi-core processor. According to one embodiment of the invention, a first set of one or more processing cores are configured to include the capability to process packets belonging to a first set of one or more packet types, and a second set of one or more processing cores are configured to include the capability to process packets belonging to a second set of one or more packet types, where the second set of packet types is a subset of the first set of packet types. Packets belonging to the first set of packet types are processed at a processing core of either the first or second set of processing cores. Packets belonging to the second set of packet types are processed at a processing core of the first set of processing cores.
1. A method for packet processing on a multi-core processor having a plurality of processing cores, the method comprising:
configuring a first set of one or more of the plurality of processing cores to include the capability to process packets belonging to a first set of one or more packet types;
configuring a second set of one or more of the plurality of processing cores to include the capability to process packets at least belonging to a second set of one or more packet types, the second set of packet types being a subset of the first set of packet types;
receiving a first packet;
determining that the first packet belongs to the second set of packet types and processing the first packet at one of the first or second set of processing cores;
receiving a second packet;
determining that the second packet does not belong to the second set of packet types and processing the second packet at one of the first set of processing cores, wherein each packet being processed includes a plurality of processing phases each identifiable by a phase identifier, and upon each processing phase being completed for a particular packet, associating the corresponding phase identifier with that packet;
receiving a third, fourth, and fifth packet, the third and fourth packet belonging to the same flow, wherein at least one of the processing phases of the processing of the third packet is required to be performed prior to one of the processing phases of the processing of the fourth packet;
assigning the third and fourth packets to different ones of the plurality of processing cores;
processing the at least one of the processing phases of the processing of the third packet and stalling the processing of the fourth packet;
upon determining that processing of the fourth packet is stalled, de-scheduling the processing of the fourth packet and allowing the processing core that was assigned to process the fourth packet to process the fifth packet; and
upon the completion of that at least one processing phase of the third packet, releasing the stalling of the processing of the fourth packet allowing one of the processing cores to process the fourth packet at the particular processing phase when de-scheduled.
2. The method of claim 1 , wherein the multi-core processor is included in a network element.
3. The method of claim 1 , wherein the multi-core processor is included in a secure router.
4. The method of claim 1 , wherein the first set of packet types includes all packets to be processed by the multi-core processor including control packets, data packets, and configuration packets.
5. The method of claim 1 , further comprising:
configuring a third set of one or more of the plurality of processing cores to include the capability to process packets at least belonging to a third set of one or more packet types, the third set of packet types being a subset of the first set of packet types and at least partially different than the second set of packet types.
6. The method of claim 1 , further comprising:
upon receiving the first and second packets, assigning the first and second packets to different ones of the processing cores based on the processing capability of those processing cores.
7. The method of claim 1 , further comprising:
upon receiving the first and second packets, assigning the first and second packets to different ones of the processing cores irrespective of the processing capability of those processing cores; and
wherein if the second packet is assigned to one of the second set of processing cores, redirecting the second packet to one of the first set of processing cores.
8. The method of claim 1 , wherein the first set of processing cores are each configured with a complete firmware image, and wherein the second set of processing cores are each configured with a subset of the complete firmware image, and wherein the second set of packet types excludes packets that require processing capabilities other than capabilities supported by the subset of the complete firmware image.
9. The method of claim 2 , wherein the first set of packet types includes control packets and packets related to network element configuration, and wherein the second set of packet types does not include control packets and packets related to network element configuration.
10. The method of claim 8 , wherein the complete firmware image includes an operating system, and wherein the subset of the complete firmware image does not include an operating system.
11. A non-transitory machine-readable storage medium that provides instructions that, if executed by a processor, will cause said processor to perform operations for packet processing on a multi-core processor having a plurality of processing cores, the operations comprising:
configuring a first set of one or more of the plurality of processing cores to include the capability to process packets belonging to a first set of one or more packet types;
configuring a second set of one or more of the plurality of processing cores to include the capability to process packets at least belonging to a second set of one or more packet types, the second set of packet types being a subset of the first set of packet types;
receiving a first packet;
determining that the first packet belongs to the second set of packet types and processing the first packet at one of the first or second set of processing cores;
receiving a second packet;
determining that the second packet does not belong to the second set of packet types and processing the second packet at one of the first set of processing cores, wherein each packet being processed includes a plurality of processing phases each identifiable by a phase identifier, and upon each processing phase being completed for a particular packet, associating the corresponding phase identifier with that packet;
receiving a third, fourth, and fifth packet, the third and fourth packet belonging to the same flow, wherein at least one of the processing phases of the processing of the third packet is required to be performed prior to one of the processing phases of the processing of the fourth packet;
assigning the third and fourth packets to different ones of the plurality of processing cores;
processing the at least one of the processing phases of the processing of the third packet and stalling the processing of the fourth packet;
upon determining that processing of the fourth packet is stalled, de-scheduling the processing of the fourth packet and allowing the processing core that was assigned to process the fourth packet to process the fifth packet; and
upon the completion of that at least one processing phase of the third packet, releasing the stalling of the processing of the fourth packet allowing one of the processing cores to process the fourth packet at the particular processing phase when de-scheduled.
12. The non-transitory machine-readable storage medium of claim 11 , wherein the multi-core processor is included in a network element.
13. The non-transitory machine-readable storage medium of claim 11 , wherein the multi-core processor is included in a secure router.
14. The non-transitory machine-readable storage medium of claim 11 , wherein the first set of packet types includes all packets to be processed by the multi-core processor including control packets, data packets, and configuration packets.
15. The non-transitory machine-readable storage medium of claim 11 , further comprising:
configuring a third set of one or more of the plurality of processing cores to include the capability to process packets at least belonging to a third set of one or more packet types, the third set of packet types being a subset of the first set of packet types and at least partially different than the second set of packet types.
16. The non-transitory machine-readable storage medium of claim 11 , further comprising:
upon receiving the first and second packets, assigning the first and second packets to different ones of the processing cores based on the processing capability of those processing cores.
17. The non-transitory machine-readable storage medium of claim 11 , further comprising:
upon receiving the first and second packets, assigning the first and second packets to different ones of the processing cores irrespective of the processing capability of those processing cores; and
wherein if the second packet is assigned to one of the second set of processing cores, redirecting the second packet to one of the first set of processing cores.
18. The non-transitory machine-readable storage medium of claim 11 , wherein the first set of processing cores are each configured with a complete firmware image, and wherein the second set of processing cores are each configured with a subset of the complete firmware image, and wherein the second set of packet types excludes packets that require processing capabilities other than capabilities supported by the subset of the complete firmware image.
19. The non-transitory machine-readable storage medium of claim 12 , wherein the first set of packet types includes control packets and packets related to network element configuration, and wherein the second set of packet types does not include control packets and packets related to network element configuration.
20. The non-transitory machine-readable storage medium of claim 18 , wherein the complete firmware image includes an operating system, and wherein the subset of the complete firmware image does not include an operating system.