IP Library Granted Patent US 7,763,926
Granted Patent B2
US 7,763,926 · App. 12/246,533 · Granted Jul 27, 2010

Semiconductor device manufacturing method and semiconductor device

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Quick Facts
Patent No.
US 7,763,926
App. No.
12/246,533
Granted
Jul 27, 2010
Kind
B2
Abstract

A technique is provided which makes it possible to achieve both of a reduction in contact resistance in a memory device and a reduction in contact resistance in a logic device even when oxidation is performed during formation of dielectric films of capacitors. Conductive barrier layers ( 82 ) are provided in the top ends of contact plugs ( 83 b ) electrically connected to ones of source/drain regions ( 59 ). Lower electrodes ( 70 ) of capacitors ( 73 ) are formed in contact with the conductive barrier layers ( 82 ) of the contact plugs ( 83 b ) and then dielectric films ( 71 ) and upper electrodes ( 72 ) of the capacitors ( 73 ) are sequentially formed. In the logic region, contact plugs ( 25 ) are formed in an upper layer so that they are in contact respectively with contact plugs ( 33 ) electrically connected to source/drain regions ( 9 ).

Claims (24)

1. A semiconductor device comprising:

a semiconductor substrate having a memory region where a memory device is formed and a logic region where a logic device is formed;

a first insulating film provided on said semiconductor substrate;

first and second contact plugs provided in said first insulating film with their respective top surfaces exposed from said first insulating film, and electrically connected to said semiconductor substrate in said memory region;

a third contact plug provided in said first insulating film with its top surface exposed from said first insulating film, and electrically connected to said semiconductor substrate in said logic region;

an MIM capacitor having a lower electrode, an upper electrode, and a dielectric film interposed therebetween, said lower electrode being in contact with the top surface of said first contact plug;

a second insulating film provided on said first insulating film and covering said MIM capacitor;

a fourth contact plug provided in said second insulating film and being in contact with said second contact plug; and

a fifth contact plug provided in said second insulating film and being in contact with said third contact plug;

said first contact plug having first conductive film below a top portion;

means for preventing the first conductive film from being oxidized during formation of the dielectric film so as to reduce contact resistance;

said second contact plug having a second conductive barrier layer in its top portion and having, in a remaining portion, a second conductive film having a higher conductivity than said second conductive barrier layer;

means for reducing contact resistance between said fourth contact plug and said semiconductor substrate;

said third contact plug having a third conductive barrier layer in its top portion and having, in a remaining portion, a third conductive film having a higher conductivity than said third conductive barrier layer;

said fifth contact plug extending into said first insulating film and being in contact with said third conductive barrier layer and a side surface of said third conductive film,

wherein a reduction in contact resistance in a logic device is achieved.

2. The semiconductor device according to claim 1 , wherein said fourth and fifth contact plugs are in contact with the entire periphery of said side surface of said second conductive film.

3. The semiconductor device according to claim 1 , further comprising:

first and second source/drain regions formed at a given distance from each other in an upper surface of said semiconductor substrate in said memory region; and

a gate structure provided on the upper surface of said semiconductor substrate between said first and second source/drain regions,

wherein said first insulating film is provided on said semiconductor substrate and covers said gate structure,

said first and second contact plugs are electrically connected respectively with said first and second source/drain regions,

said fourth contact plug has its top surface exposed from said second insulating film and

said semiconductor device further comprises a bit line provided on said second insulating film and being in contact with said fourth contact plug.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 053654 FRAME: 0254. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jun 10, 2021
From: STARBOARD VALUE INTERMEDIATE FUND LP
To: ACACIA RESEARCH GROUP LLC
Reel/Frame 057454/0045 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR NAME PREVIOUSLY RECORDED ON REEL 052853 FRAME 0153. ASSIGNOR(S) HEREBY CONFIRMS THE PATENT SECURITY AGREEMENT. Recorded Mar 2, 2021
From: ACACIA RESEARCH GROUP LLC
To: STARBOARD VALUE INTERMEDIATE FUND LP, AS COLLATERAL AGENT
Reel/Frame 056775/0066 →
RELEASE OF SECURITY INTEREST IN PATENTS Recorded Jul 8, 2020
From: STARBOARD VALUE INTERMEDIATE FUND LP
To: ACACIA RESEARCH GROUP LLC; AMERICAN VEHICULAR SCIENCES LLC; BONUTTI SKELETAL INNOVATIONS LLC; CELLULAR COMMUNICATIONS EQUIPMENT LLC; INNOVATIVE DISPLAY TECHNOLOGIES LLC; LIFEPORT SCIENCES LLC; LIMESTONE MEMORY SYSTEMS LLC; MOBILE ENHANCEMENT SOLUTIONS LLC; MONARCH NETWORKING SOLUTIONS LLC; NEXUS DISPLAY TECHNOLOGIES LLC; PARTHENON UNIFIED MEMORY ARCHITECTURE LLC; R2 SOLUTIONS LLC; SAINT LAWRENCE COMMUNICATIONS LLC; STINGRAY IP SOLUTIONS LLC; SUPER INTERCONNECT TECHNOLOGIES LLC; TELECONFERENCE SYSTEMS LLC; UNIFICATION TECHNOLOGIES LLC
Reel/Frame 053654/0254 →
PATENT SECURITY AGREEMENT Recorded Jun 5, 2020
From: ACACIA RESEARCH GROUP LLC; AMERICAN VEHICULAR SCIENCES LLC; BONUTTI SKELETAL INNOVATIONS LLC; CELLULAR COMMUNICATIONS EQUIPMENT LLC; INNOVATIVE DISPLAY TECHNOLOGIES LLC; LIFEPORT SCIENCES LLC; LIMESTONE MEMORY SYSTEMS LLC; MERTON ACQUISITION HOLDCO LLC; MOBILE ENHANCEMENT SOLUTIONS LLC; MONARCH NETWORKING SOLUTIONS LLC; NEXUS DISPLAY TECHNOLOGIES LLC; PARTHENON UNIFIED MEMORY ARCHITECTURE LLC; R2 SOLUTIONS LLC; SAINT LAWRENCE COMMUNICATIONS LLC; STINGRAY IP SOLUTIONS LLC; SUPER INTERCONNECT TECHNOLOGIES LLC; TELECONFERENCE SYSTEMS LLC; UNIFICATION TECHNOLOGIES LLC
To: STARBOARD VALUE INTERMEDIATE FUND LP, AS COLLATERAL AGENT
Reel/Frame 052853/0153 →
CHANGE OF NAME Recorded Sep 1, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 024915/0526 →
MERGER Recorded Sep 1, 2010
From: RENESAS TECHNOLOGY CORP.
To: NEC ELECTRONICS CORPORATION
Reel/Frame 024915/0556 →