Modulation coding
View Patent ↗Methods and apparatus are provided for modulation coding of input data. In a first scheme, a modulation encoder applies a modulation code to input data to produce an (L,K)-constrained encoded bit-sequence, where K is maximum run-length of 0's, and L is the maximum run-length of 0's in each of the odd and even interleaves of the encoded bit-sequence. Then, a precoder effects 1/(1⊕D 4 ) preceding of the encoded bit-sequence. In a second scheme, a modulation encoder applies a modulation code to the input data to produce a K-constrained encoded bit-sequence. In this scheme, a precoder then effects 1/(1⊕D⊕D 2 ⊕D 3 ) preceding of the encoded bit-sequence. In both schemes, the effect of the precoder is to produce a precoded sequence in which, in addition to other constraints, the maximum length of the variable frequency oscillator pattern is constrained to a predetermined value C VFO .
1. An apparatus for modulation coding of input data, the apparatus comprising:
a modulation encoder for applying a modulation code to the input data to produce an encoded bit-sequence in which the maximum run-length of 0's is constrained to a predetermined value K and the maximum run-length of 0's in each of the odd and even interleaves of the encoded bit-sequence is constrained to a predetermined value L; and
a precoder for effecting 1/(1⊕D 4 ) precoding of the encoded bit-sequence to produce a precoded sequence in which the maximum length of the variable frequency oscillator pattern is constrained to a predetermined value C VFO .
2. The apparatus of claim 1 , wherein the precoder comprises a single precoder stage for effecting the 1/(1⊕D 4 ) precoding.
3. The apparatus of claim 1 , wherein the precoder comprises a plurality of precoder stages (which together effect the 1/(1⊕D 4 ) precoding.
4. The apparatus of claim 1 , wherein C VFO =K+4.
5. The apparatus of claim 1 , wherein the precoder produces a precoded sequence in which at least one of the constraints is satisfied:
(a) the maximum run-length of 0's is constrained to a predetermined value c 0 ;
(b) the maximum run-length of 1's is constrained to a predetermined value c 1 ;
(c) the maximum number of alternating bits is constrained to a predetermined value c a ;
(d) the maximum run-length of 0's in each of the odd and even interleaves is constrained to a predetermined value i 0 ; and
(e) the maximum run-length of 1's in each of the odd and even interleaves is constrained to a predetermined value i 1 ;
is satisfied.
6. The apparatus of claim 4 , wherein all of the constraints (a) to (e) are satisfied in the precoded sequence.
7. The apparatus of claim 4 , wherein the values of c 0 , c 1 , and c a are equal to K+4 and the values of i 0 and i 1 are equal to L+2.
8. The apparatus of claim 3 , wherein the precoder comprises a first precoder stage for effecting 1/(1⊕D⊕D 2 ⊕D 3 ) precoding of the encoded bit-sequence to produce a partially-precoded bit sequence, and a second precoder stage for effecting 1/(1⊕D) precoding of the partially-precoded bit sequence to produce said precoded sequence.
9. The apparatus of claim 8 , further comprising an ECC encoder for effecting error-correction coding of the partially-precoded bit sequence prior to said 1/(1⊕D) precoding.
10. The apparatus of claim 9 , wherein the ECC encoder is adapted to effect partial interleaving of parity symbols in the partially-precoded bit sequence.
11. An apparatus for modulation coding of input data, the apparatus comprising:
a modulation encoder for applying a modulation code to the input data to produce an encoded bit-sequence in which the maximum run-length of 0's is constrained to a predetermined value K; and
a precoder for effecting 1/(1⊕D⊕D 2 ⊕D 3 ) precoding of the encoded bit-sequence to produce a precoded sequence in which the maximum length of the variable frequency oscillator pattern is constrained to a predetermined value C VFO .
12. The apparatus of claim 11 , wherein the precoder comprises a single precoder stage for effecting the 1/(1⊕D⊕D 2 ⊕D 3 ) precoding.
13. The apparatus of claim 11 , wherein the precoder comprises a plurality of precoder stages which together effect the 1/(1⊕D⊕D 2 ⊕D 3 ) precoding.
14. The apparatus of claim 11 , wherein the modulation encoder is adapted to apply a modulation code such that the maximum run-length of 0's in each of the odd and even interleaves of the encoded bit-sequence is constrained to a predetermined value L, the arrangement being such that the precoder produces a precoded sequence in which the data sequence separator pattern is excluded.
15. The apparatus of claim 11 , wherein C VFO =K+3.
16. The apparatus of claim 11 , wherein the precoder produces a precoded sequence in which at least one of the following constraints is satisfied:
(a) the maximum run-length of 0's is constrained to a predetermined value c 0 ;
(b) the maximum run-length of 1's is constrained to a predetermined value c 1 ; and
(c) the maximum number of alternating bits is constrained to a predetermined value c a .
17. The apparatus of claim 16 , wherein all of the constraints (a) to (c) are satisfied in the precoded sequence.
18. The apparatus of claim 17 , wherein the values of c 0 , c 1 , and c a are equal to K+3.
19. The apparatus of claim 14 , wherein the modulation encoder is adapted to apply a rate X/Y partitioned block code to produce the encoded bit-sequence by:
partitioning each of a succession of X-bit input data words into a plurality of blocks of bits; and
for each X-bit data word, encoding at least one of said blocks in accordance with a finite state coding scheme, thereby to produce a Y-bit codeword from the X-bit data word.
20. The apparatus of claim 14 , wherein the modulation encoder is adapted to apply an enumerative modulation code to the input data.
21. The apparatus of claim 20 , wherein the modulation encoder is adapted to apply a generalized Fibonacci code in each of odd and even interleaves of the input data to produce the encoded bit-sequence.
22. A method for modulation coding of input data, the method comprising:
applying a modulation code to the input data to produce an encoded bit-sequence in which the maximum run-length of 0's is constrained to a predetermined value K and the maximum run-length of 0's in each of the odd and even interleaves of the encoded bit-sequence is constrained to a predetermined value L; and
effecting 1/(1⊕D 4 ) precoding of the encoded bit-sequence to produce a precoded sequence in which the maximum length of the variable frequency oscillator pattern is constrained to a predetermined value C VFO .
23. The method of claim 22 , wherein C VFO =K+4.
24. The method of claim 22 , wherein the precoding is effected such that in the precoded sequence:
(a) the maximum run-length of 0's is constrained to a predetermined value c 0 ;
(b) the maximum run-length of 1's is constrained to a predetermined value c 1 ;
(c) the maximum number of alternating bits is constrained to a predetermined value c a ;
(d) the maximum run-length of 0's in each of the odd and even interleaves is constrained to a predetermined value i 0 ; and
(e) the maximum run-length of 1's in each of the odd and even interleaves is constrained to a predetermined value i 1 .
25. The method of claim 24 , wherein the precoding is effected such that the values of c 0 , c 1 , and c a are equal to K+4 and the values of i 0 and i 1 are equal to L+2.