Methods and apparatus for differentiated services over a packet-based network
Methods and apparatus for the provision of differentiated services in a packet-based network may be provided in a communications device such as a switch or router having input ports and output ports. Each output port is associated with a set of configurable queues that store incoming data packets from one or more input ports. A scheduling mechanism retrieves data packets from individual queues in accord with a specified configuration, providing both pure priority and proportionate de-queuing to achieve a guaranteed QoS over a connectionless network.
1. A hierarchical packet-buffering system of memory structures for processing packets in a network, the network having a network bandwidth, the system comprising:
a first memory including one or more first packet buffers configured to receive data packets from the network, each of the one or more first packet buffers having a first packet-buffer bandwidth and a first packet-buffer depth, wherein a sum of first packet-buffer bandwidths is equal to or greater than the network bandwidth; and
a second memory different from the first memory and including one or more second packet buffers configured to receive packets from at least one of the one or more first packet buffers, each of the one or more second packet buffers having a second packet-buffer bandwidth and a second packet-buffer depth and being organized as a plurality of queues, each of the plurality of queues being configurable, by a configuration parameter stored in memory, to independently operate in one of a fairness-based mode and a priority based-mode, wherein a sum of the second packet-buffer depths is equal to or greater than a sum of first packet-buffer depths of the at least one of the one or more first packet buffers and a sum of the second packet-buffer bandwidths is equal to or greater than a sum of first packet-buffer bandwidths of the at least one of the one or more first packet buffers.
2. The system according to claim 1 , wherein the one or more first packet buffers comprise a packet buffer embedded in an ASIC.
3. The system according to claim 1 , wherein each of the one or more second packet buffers comprises field configurable memory elements.
4. The system according to claim 1 , wherein the first memory is composed of a first memory type and the second memory is composed of a second memory type, the second memory type having performance characteristics substantially different from that of the first memory type.
5. The system according to claim 1 , wherein the one or more first packet buffers and the one or more second packet buffers are implemented in a fully connected mesh architecture having a plurality of input ports and a plurality of output ports, each input port being continuously connected to a corresponding output port.
6. The system according to claim 1 , wherein the one or more first packet buffers and the one or more second packet buffers are implemented in a partially connected mesh architecture having a plurality of input ports and a plurality of output ports, at least one of the input ports being switchably connected to at least one of the output ports.
7. The system according to claim 1 , wherein each of the one or more second packet buffers has a priority level and the system is configured to transmit packets according to the priority level of each of the one or more second packet buffers.
8. The system according to claim 1 , further comprising a scheduler in communication with the one or more second packet buffers, the scheduler configured to donate bandwidth from one of the one or more second packet buffers with a first priority level to another of the one or more second packet buffers with a second priority level, wherein the first priority level is higher than the second priority level.
9. The system according to claim 8 , further comprising a scheduler in communication with the one or more second packet buffers, the scheduler configured to donate bandwidth from one of the one or more second packet buffers with a first priority level to another of the one or more second packet buffers with a second priority level, wherein the first priority level is lower than the second priority level.
10. The system according to claim 1 , further comprising a scheduler in communication with the one or more second packet buffers, the scheduler configured to independently schedule packets on a pure priority basis.
11. The system according to claim 1 , further comprising a scheduler in communication with the one or more second packet buffers, the scheduler configured to independently schedule packets using a weighted fair queuing technique.
12. The system according to claim 1 , further comprising a scheduler in communication with the one or more second packet buffers, the scheduler configured to independently schedule packets using a random early detection technique.
13. The system according to claim 1 , further comprising a scheduler in communication with the one or more second packet buffers, the scheduler configured to independently schedule packets using a weighted random early detection technique.
14. The system according to claim 1 , further comprising a scheduler in communication with the one or more second packet buffers, the scheduler configured to independently schedule packets using a bandwidth donation technique.
15. The system according to claim 1 , further comprising a scheduler in communication with the one or more second packet buffers, the scheduler configured to independently schedule packets by using a combination of techniques selected from pure priority, weighted fair queuing, random early detection, weighted random early detection, and bandwidth donation.
16. A hierarchical packet-buffering system of memory structures for processing packets in a network, the network having a network bandwidth, the system comprising:
a first memory including one or more first packet buffers configured to receive data packets from the network, each of the one or more first packet buffers having a first packet-buffer bandwidth and a first packet-buffer depth, wherein a sum of first packet-buffer bandwidths is equal to or greater than the network bandwidth;
a second memory different from the first memory and including one or more second packet buffers configured to receive packets from at least one of the one or more first packet buffers, each of the one or more second packet buffers having a second packet-buffer bandwidth and a second packet-buffer depth, wherein a sum of the second packet-buffer depths is equal to or greater than a sum of first packet-buffer depths of the at least one of the one or more first packet buffers and a sum of the second packet-buffer bandwidths is equal to or greater than a sum of the first packet-buffer bandwidths of the at least one of the one or more first packet buffers; and
one or more other packet buffers configured to receive packets from one or more previous packet buffers, each of the one or more other packet buffers being organized as a plurality of queues, each of the plurality of queues being configurable, by a configuration parameter stored in memory, to independently operate in one of a fairness-based mode and a priority based-mode.
17. The system according to claim 16 , wherein the first packet buffer comprises a packet buffer embedded in an ASIC.
18. The system according to claim 16 , wherein the one or more previous packet buffers include at least one of the one or more second packet buffers.
19. The system according to claim 16 , wherein the one or more previous packet buffers include one or more third packet buffers configured to receive packets from at least one of the one or more second packet buffers.
20. The system according to claim 16 , further comprising a scheduler in communication with the one or more other packet buffers, the scheduler configured to independently schedule packets by using at least one technique selected from pure priority, weighted fair queuing, random early detection, weighted random early detection, and bandwidth donation.