Analog to digital converter with dynamic power configuration
View Patent ↗In an embodiment, an analog to digital converter (ADC) has a dynamic power circuit. The ADC has a track-and-hold circuit with an output and a track mode. The ADC also has a comparator with an input. A preamplifier is coupled between the track-and-hold output and the comparator input. At least one of a preamplifier current and a comparator current are limited during the track mode to reduce ADC power consumption.
1. An analog to digital converter (ADC), comprising:
a track-and-hold circuit having a track mode; and
a comparator coupled to the track-and-hold circuit;
wherein a comparator current is limited during the track mode.
2. The ADC of claim 1 , further comprising a preamplifier coupled between the track-and-hold circuit and the comparator, wherein a preamplifier current is limited during the track mode.
3. The ADC of claim 2 , further comprising a current control transistor coupled between ground and the preamplifier, wherein the current control transistor is configured to resist current flow during the track mode.
4. The ADC of claim 3 , further comprising:
a second transistor coupled between a node and a first voltage source;
a third transistor coupled between the node and a second voltage source,
wherein the node is coupled to control the current control transistor; and
an inverter, wherein an inverter input is configured to control the second transistor and an inverter output is configured to control the third transistor.
5. The ADC of claim 2 , wherein at least one of the track-and-hold circuit, the preamplifier, and the comparator are deposited on a substrate.
6. The ADC of claim 1 , further comprising a transistor coupled between a power source and a comparator output, wherein the transistor is configured to conduct during the track mode.
7. The ADC of claim 6 , further comprising a control circuit coupled between the track-and-hold circuit and the transistor.
8. The ADC of claim 1 , further comprising a current control transistor coupled between ground and the comparator, wherein the transistor is configured to resist current flow during the track mode.
9. The ADC of claim 8 , further comprising:
a second transistor coupled between a node and a first voltage source;
a third transistor coupled between the node and a second voltage source,
wherein the node is coupled to control the current control transistor; and
an inverter, wherein an inverter input is configured to control the second transistor and an inverter output is configured to control the third transistor.
10. The ADC of claim 1 , further comprising:
a latch circuit coupled to a comparator output; and
a transistor coupled between the latch circuit and a comparator input,
wherein the transistor is configured to reduce the comparator current during the track mode.
11. A method for reducing power consumption in an analog-to-digital converter (ADC) having a track-and-hold circuit, comprising:
determining if the track-and-hold circuit is in a track mode; and
adjusting a current flow in the ADC to reduce ADC power consumption during the track mode.
12. The method of claim 11 , wherein the adjusting further comprises limiting the current flow through a differential pair.
13. The method of claim 11 , wherein the adjusting further comprises selectively coupling resistance to vary a load in the ADC.
14. The method of claim 11 , wherein the adjusting further comprises shorting a load in the ADC.
15. The method of claim 11 , wherein the adjusting further comprises selecting a transistor control voltage to adjust the current flow.
16. The method of claim 11 , wherein the adjusting further comprises reducing the current flow in at least one of a preamplifier and a comparator.
17. The method of claim 11 , further comprising suppressing reference ladder noise during the track mode.
18. The method of claim 11 , further comprising resetting at least one of a preamplifier and a comparator during the track mode.
19. An analog to digital converter (ADC), comprising:
means for determining if the track-and-hold circuit is in a track mode; and
means for adjusting a current flow in the ADC to reduce ADC power consumption during the track mode.
20. The ADC of claim 19 , wherein the means for adjusting further comprises means for limiting the current flow through a differential pair.
21. The ADC of claim 19 , wherein the means for adjusting further comprises means for selectively coupling resistance to vary a load in the ADC.
22. The ADC of claim 19 , wherein the means for adjusting further comprises means for shorting a load in the ADC.
23. The ADC of claim 19 , wherein the means for adjusting further comprises means for selecting a transistor control voltage to adjust the current flow.
24. The ADC of claim 19 , wherein the means for adjusting further comprises means for reducing the current flow in at least one of a preamplifier and a comparator.
25. The ADC of claim 19 , further comprising means for suppressing reference ladder noise during the track mode.
26. The ADC of claim 19 , further comprising means for resetting at least one of a preamplifier and a comparator during the track mode.