IP Library Granted Patent US 7,643,315
Granted Patent B2
US 7,643,315 · App. 12/313,344 · Granted Jan 5, 2010

Programmable feedback voltage pulse sampling for switched power supplies

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Quick Facts
Patent No.
US 7,643,315
App. No.
12/313,344
Granted
Jan 5, 2010
Kind
B2
Abstract

Disclosed is a method and apparatus that includes a power supply having a primary coil and a secondary coil. The secondary coil generates an output voltage and a feedback voltage related to the output voltage. The feedback voltage is sampled at a time instant that is digitally controllable. The output voltage is determined from the feedback voltage.

Claims (28)

1. A circuit-implemented method for determining an output voltage of an isolated flyback power supply having a primary coil and a secondary coil, said secondary coil for generating said output voltage and for inductively generating a feedback voltage related to said output voltage, said method comprising:

determining a digitally controllable time instant using a time delay based on a value stored in a register;

sampling said feedback voltage at the digitally controllable time instant; and

determining said output voltage from said sampled feedback voltage.

2. The method of claim 1 wherein said time instant is specified by a register.

3. The method of claim 1 comprising digitally controlling a switch that controls said feedback voltage.

4. The method of claim 1 wherein said feedback voltage spikes before leveling off into a plateau.

5. The method of claim 4 wherein said sampling said feedback voltage occurs at the start of said plateau.

6. A circuit-implemented method for an isolated flyback power supply having (a) on a primary side, (i) a primary coil, (ii) a controller having a clock signal having a period, and (iii) a switch connected to the primary coil and controlled by the controller and (b) on a secondary side, a secondary coil, the method comprising:

setting a delay parameter D corresponding to an integer multiple of the period of the clock signal;

configuring, based on the delay parameter, the controller to sample, on the primary side, a feedback voltage, proportional to a voltage across the secondary coil, D periods of the clock signal after a turn-off time;

at a turn-on time before the turn-off time, turning on the switch;

at the turn-off time, turning off the switch to generate the feedback voltage; and

sampling the feedback voltage D periods of the clock signal following the turn-off time.

7. The method of claim 6 , wherein the configuring step comprises configuring a digital delay chain to delay the sampling by D periods of the clock signal.

8. The method of claim 6 , wherein the sampling step comprises analog-to-digital conversion.

9. The method of claim 8 , wherein the analog-to-digital conversion comprises converting a value of the feedback voltage into a digital word for further digital processing.

10. The method of claim 6 , wherein the controller is configured to sample the feedback voltage exactly once between the turn-off time and a subsequent turn-on time.

11. The method of claim 6 , wherein the configuring step is performed by a high-level control and software interface.

12. The method of claim 11 , wherein the high-level control and software interface comprises a set of registers, wherein the delay parameter is stored in the set of registers.

13. The method of claim 6 , further comprising dynamically changing the delay parameter D.

14. The method of claim 6 , wherein:

the configuring step comprises configuring a digital delay chain to delay the sampling by D periods of the clock signal;

the sampling step comprises analog-to-digital conversion;

the analog-to-digital conversion comprises converting a value of the feedback voltage into a digital word for further digital processing;

the controller is configured to sample the feedback voltage exactly once between the turn-off time and a subsequent turn-on time;

the configuring step is performed by a high-level control and software (HLCS) interface; and

the HLCS interface comprises a set of registers, wherein the delay parameter is stored in the set of registers.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER PREVIOUSLY RECORDED AT REEL: 047195 FRAME: 0827. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Nov 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047924/0571 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047195/0827 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035365/0634 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 7, 2009
From: BLAHA, MATTHEW; MOLINA, ALBERT; QUIRK, PATRICK J.; SAIBI, FADI
To: AGERE SYSTEMS INC.
Reel/Frame 022067/0666 →