Semiconductor device and data processor
Synchronization between command and address signals commonly coupled to a plurality of memory devices to be operated in parallel and a clock signal coupled to the memory devices is achieved, while suppressing an increase in the clock wiring length. A semiconductor device has a data processing device mounted on a wiring substrate and a plurality of memory devices accessed in parallel by the data processing device. The data processing device outputs the command and address signals as a first frequency from command and address terminals, and outputs a clock signal as a second frequency from a clock terminal. The second frequency is set to multiple times of the first frequency, and an output timing equal to or earlier than a cycle starting phase of the clock signal output from the clock terminal can be selected to the command and address signals output from the command and address terminals.
1. A semiconductor device, comprising:
a wiring substrate;
a data processing device mounted on the wiring substrate; and
a plurality of memory devices mounted on the wiring substrate and coupled to the data processing device,
wherein the data processing device includes:
a plurality of data system terminals coupled to the memory devices;
a plurality of command and address terminals,
a plurality of clock terminals; and
a memory controller for controlling inputs and outputs of these terminals,
wherein the wiring substrate includes:
an individual wiring coupling the data system terminal to the memory devices, respectively;
a first branch wiring branching each of the command and address terminals along its way, and commonly coupling the branched ones to the memory devices, respectively; and
a second branch wiring branching the clock terminal along its way, and coupling the branched ones to the memory devices,
wherein the second branch wiring having the number of branches;
wherein the number of branches of the second branch wiring is less than or equal to that of the first branch wiring;
wherein the memory controller outputs command and address signals as a first frequency from the command and address terminals, and outputs a clock signal as a second frequency from the clock terminal;
wherein the second frequency is set to multiple times of the first frequency; and
wherein an output timing equal to or earlier than a cycle starting phase of the clock signal output from the clock terminal can be selected to the command and address signals output from the command and address terminals.
2. The semiconductor device according to claim 1 , wherein the data processing device selects the early output timing from a plurality of output timings.
3. The semiconductor device according to claim 2 , wherein the data processing device initializes an output timing of the command and address signals in a power-on-reset processing.
4. The semiconductor device according to claim 1 , wherein:
the memory controller includes a variable delay circuit; and
the smaller a delay time set in the variable delay circuit becomes, the earlier the command and address signal output from the command and address terminal is output than the cycle starting phase of the clock signal output from the clock terminal.
5. The semiconductor device according to claim 2 , wherein:
the data processing device includes a CPU and a control register accessible by the CPU; and
the delay time of the variable delay circuit is determined by control data written into the control register.
6. The semiconductor device according to claim 4 , wherein the variable delay circuit is positioned in a transmission path of the command and address signal output from the command and address terminal.
7. The semiconductor device according to claim 4 , wherein the variable delay circuit is positioned in a transmission path of a latch clock of a latch circuit for latching the command and address signal output from the command and address terminal.
8. A semiconductor device, comprising:
a wiring substrate,
a data processing device mounted on the wiring substrate; and
four memory devices mounted on the wiring substrate and coupled to the data processing device,
wherein the data processing device includes:
a data system terminal coupled to the four memory devices, separately;
command and address terminals commonly coupled to the four memory devices;
a first clock terminal coupled to two of the four memory devices;
a second clock terminal coupled to the other two of the four memory devices; and
a memory controller for controlling inputs and outputs of these terminals,
wherein the wiring substrate includes:
a data system wiring for coupling the data system terminal to the memory device in one-to-one correspondence;
a command and address wiring branching into four along its way, with the command and address terminals as a base point, to be commonly coupled to the four memory devices;
a first clock wiring branching into two along its way, with the first clock terminal as a base point, to be commonly coupled to the two corresponding memory devices; and
a second clock wiring branching into two along its way, with the second clock terminal as a base point, to be commonly coupled to the two corresponding memory devices;
wherein when controlling the four memory devices, the memory controller outputs command and address signals as a first frequency from the command and address terminals, and outputs a clock signal as a second frequency from the first clock terminal and the second clock terminal;
wherein the second frequency is set to multiple times of the first frequency; and
wherein an output timing earlier than a cycle starting phase of clock signals output from the first clock terminal and the second clock terminal can be selected to the command and address signals output from the command and address terminals.
9. The semiconductor device according to claim 8 , wherein:
the data system terminal, the command and address terminal, and the first and second clock terminals are arranged separately on both sides across a corner portion of the data processing device;
the data system terminal is spaced apart from the corner portion as compared with the command and address terminal and the first and second clock terminals;
the two memory devices are opposingly mounted on both sides across the corner portion of the data processing device, in one surface of the wiring substrate;
the other two memory devices are mounted in the other surface of the wiring substrate positioned on a back side of the two memory devices;
the data system wiring extends toward a corresponding memory device from each side across the corner portion of the data processing device; and
the command and address wiring and the first and second clock wirings branch along their ways, with the corner portion of the data processing device as a base point, and extend toward each of the memory devices.
10. The semiconductor device according to claim 9 , wherein:
each of the memory devices is a JEDEC-compliant DDR2-SDRAM having 8-bit memory data terminals; and
a short side near the data terminal of the memory device is arranged opposite to a side of the data processing device.
11. A semiconductor device, comprising:
a wiring substrate,
a data processing device mounted on the wiring substrate; and
two memory devices mounted on the wiring substrate and coupled to the data processing device,
wherein the data processing device includes:
a data system terminal coupled to the two memory devices, separately;
command and address terminals commonly coupled to the two memory devices;
a clock terminal coupled to the two memory devices; and
a memory controller for controlling inputs and outputs of these terminals,
wherein the wiring substrate includes:
a data system wiring for coupling the data system terminal to the memory device in one-to-one correspondence;
a command and address wiring branching into two along its way to commonly couple the command and address terminals to the two memory devices; and
a clock wiring branching into two along its way to commonly couple the clock terminal to the two corresponding memory devices;
wherein when controlling the two memory devices, the memory controller outputs command and address signals as a first frequency from the command and address terminals, and outputs a clock signal as a second frequency from the clock terminal;
wherein the second frequency is set to multiple times of the first frequency; and
wherein an output timing equal to or earlier than a cycle starting phase of the clock signal output from the clock terminal can be selected to the command and address signals output from the command and address terminals.
12. The semiconductor device according to claim 11 , wherein:
the data system terminal, the command and address terminal, and the first and second clock terminals are arranged separately on both sides across a corner portion of the data processing device;
the data system terminal is spaced apart from the corner portion as compared with the command and address terminal and the first and second clock terminals;
the two memory devices are opposingly mounted on both sides across the corner portion of the data processing device, in one surface of the wiring substrate;
the data system wiring extends toward a corresponding memory device from each side across the corner portion of the data processing device; and
the command and address wiring and the first and second clock wirings branch along their ways, with the corner portion of the data processing device as a base point, and extend toward each of the memory devices.
13. The semiconductor device according to claim 12 , wherein:
each of the memory devices is a JEDEC-compliant DDR2-SDRAM having 16-bit memory data terminals; and
a long side of the memory device is arranged opposite to a side of the data processing device.
14. A data processor, comprising:
a plurality of data system terminals, command and address terminals and clock terminals each coupled to a memory device;
a memory controller for controlling the data system terminals, the command and address terminals, and the clock terminals, and
a CPU for controlling the memory controller, wherein:
the memory controller outputs a command and address signal at a first frequency from the command and address terminal and outputs a clock signal at a second frequency from the clock terminal;
the second frequency is set to multiple times of the first frequency; and
an output timing equal to or earlier than a cycle starting phase of the clock signal output from the clock terminal can be selected to the command and address signal output from the command and address terminal.
15. The semiconductor device according to claim 14 , wherein the memory controller selects the early output timing from a plurality of output timings.
16. The semiconductor device according to claim 15 , wherein the CPU initializes a selected status of output timing for the command and address signal by the memory controller, in a power-on-reset processing.
17. The data processor according to claim 15 , wherein:
the memory controller includes a variable delay circuit; and
the smaller a delay time set in the variable delay circuit becomes, the earlier the command and address signal output from the command and address terminal is output than the cycle starting phase of the clock signal output from the clock terminal.
18. The data processor according to claim 17 , further comprising a control register accessible by the CPU, wherein a delay time of the variable delay circuit is determined by control data written into the control register.
19. The data processor according to claim 17 , wherein the variable delay circuit is positioned in a transmission path of the command and address signal output from the command and address terminal.
20. The data processor according to claim 17 , wherein the variable delay circuit is positioned in a transmission path of a latch clock of a latch circuit for latching the command and address signal output from the command and address terminal.