Semiconductor device and method for producing the same
The semiconductor device includes the concentration of the impurity of the first conductivity type in a doped channel layer of a first conductivity type in the pass transistor is set at a relatively low value, and pocket regions of the first conductivity type in a pass transistor are formed so as to be relatively shallow with a relatively high impurity concentration.
1. A semiconductor device comprising:
first transistors, second transistors, and third transistors lower in threshold voltage than at least the second transistors;
each of the first transistors including first source/drain diffusion layers of a second conductivity type and a first doped channel layer of a first conductivity type arranged therebetween and formed in a semiconductor substrate, first source/drain diffusion layers, first pocket regions of the first conductivity type formed between the first doped channel layer and the first source/drain diffusion layers, a first gate insulating layer formed on the first doped channel layer, a first gate electrode formed on the first gate insulating layer;
each of the second transistors including second source/drain diffusion layers of the second conductivity type and a second doped channel layer of the first conductivity type arranged therebetween and formed in the semiconductor substrate, second pocket regions of the first conductivity type formed between the second doped channel layer and the second source/drain diffusion layers, a second gate insulating layer formed on the second doped channel layer, and a second gate electrode formed on the second gate insulating layer;
each of the third transistors including third source/drain diffusion layers of the second conductivity type and a third doped channel layer of the first conductivity type arranged therebetween and formed in the semiconductor substrate, third pocket regions of the first conductivity type formed between the third doped channel layer and the third source/drain diffusion layers, a third gate insulating formed on the third doped channel layer, and a third gate electrode formed on the third gate insulating layer;
a peak concentration of the first conductivity type impurity under a center portion of the first gate electrode being lower than a peak concentration of the first conductivity type impurity under a center portion of the second gate electrode and not higher than a peak concentration of the first conductivity type impurity under a center portion of the third gate electrode; and
a peak concentration of the first conductivity type impurity under an edge portion of the first gate electrode being higher than a peak concentration of the first conductivity type impurity under an edge portion of the second gate electrode and higher than a peak concentration of the first conductivity type impurity under an edge portion of the third gate electrode.
2. A semiconductor device according to claim 1 , wherein a depth of the concentration peak of the first conductivity type impurity under the edge portion of the first gate electrode is smaller than a depth of the concentration peak of the first conductivity type impurity under the edge portion of the second gate electrode and smaller than a depth of the concentration peak of the first conductivity type impurity under the edge portion of the third gate electrode.
3. A semiconductor device according to claim 1 , wherein a thickness of the first gate insulating layer, a thickness of the second gate insulating layer and a thickness of the third gate insulating layer are at least substantially equal.
4. A semiconductor device according to claim 1 , wherein:
the first transistors are provided in switch matrices which set routes of signals; and
the second transistors and the third transistors are provided in logic blocks.
5. A semiconductor device comprising:
first transistors, second transistors, and third transistors lower in threshold voltage than at least the second transistors;
each transistor including a gate electrode, a gate insulating layer, a channel region, the channel region being formed in a semiconductor substrate;
peak concentrations of a first conductivity type impurity under center portions of the gate electrodes of the first transistors being lower than peak concentrations of the first conductivity type impurity under center portions of the gate electrodes of the second transistors and not higher than peak concentrations of the first conductivity type impurity under center portions of the gate electrodes of the third transistors; and
peak concentrations of the first conductivity type impurity under edge portions of the first gate electrodes being higher than peak concentrations of the first conductivity type impurity under edge portions of the second gate electrodes and higher than peak concentrations of the first conductivity type impurity under edge portions of the third gate electrodes.
6. A semiconductor device according to claim 5 , wherein a depth of the concentration peak of the first conductivity type impurity under the edge portion of the first gate electrode is smaller than a depth of the concentration peak of the first conductivity type impurity under the edge portion of the second gate electrode and smaller than a depth of the concentration peak of the first conductivity type impurity under the edge portion of the third gate electrode.
7. A semiconductor device according to claim 5 , wherein a thickness of the first gate insulating layer, a thickness of the second gate insulating layer and a thickness of the third gate insulating layer are at least substantially equal.
8. A semiconductor device according to claim 5 , wherein:
the first transistors are provided in switch matrices which set routes of signals; and
the second transistors and the third transistors are provided in logic blocks.