Fabrication method of semiconductor device
A fabrication method of a semiconductor device includes: forming a gate insulating film and a gate electrode on an N type well; forming first source/drain regions by implanting a first element in regions of the N type well on both sides of the gate electrode, the first element being larger than silicon and exhibiting P type conductivity; forming second source/drain regions by implanting a second element in the regions of the N type well on the both sides of the gate electrode, the second element being smaller than silicon and exhibiting P type conductivity; and forming a metal silicide layer on the source/drain regions.
1. A fabrication method of a semiconductor device which has a P channel type MIS transistor including a gate insulating film, a gate electrode, source/drain regions composed of first source/drain regions and second source/drain regions, and a metal silicide layer, the fabrication method comprising:
(a) preparing a semiconductor substrate including an N type well surrounded by an isolation region;
(b) forming the gate electrode on the N type well, with the gate insulating film interposed therebetween;
(c) forming the first source/drain regions by implanting a first element in regions of the N type well on both sides of the gate electrode, the first element being larger than silicon and exhibiting P type conductivity;
(d) forming the second source/drain regions by implanting a second element in the regions of the N type well on the both sides of the gate electrode, the second element being smaller than silicon and exhibiting P type conductivity; and
(e) forming the metal silicide layer on the source/drain regions.
2. The method of claim 1 , wherein a gate length of the gate electrode formed at (b) is 100 nm or less.
3. The method of claim 1 , wherein
the first element is indium or gallium, and
the second element is boron.
4. The method of claim 1 , wherein the metal silicide layer is composed of nickel silicide.
5. The method of claim 1 , further comprising:
(f) forming extension regions in the regions of the N type well on the both sides of the gate electrode by implanting a P type impurity using the gate electrode as a mask, the extension regions having a P type impurity concentration lower than a P type impurity concentration of the source/drain regions; and
(g) forming a side wall on side faces of the gate insulating film and the gate electrode,
wherein at (c) and (d) the ion implantation is carried out using the gate electrode and the side wall as a mask.
6. The method of claim 1 , wherein
at (c) the first element is implanted with an acceleration energy of from 19 keV to 40 keV, both inclusive, and a dose of from 1×10 14 cm −2 to 1×10 16 cm −2 , both inclusive.
7. The method of claim 1 , wherein
the first and second source/drain regions are formed such that a depth of the first source/drain regions is deeper than a depth of the second source/drain regions.
8. The method of claim 1 , wherein
the metal silicide layer formed at (e) is composed of nickel silicide to which at least one of platinum, aluminum, copper, erbium, and palladium is added.