Semiconductor memory device and a method of manufacturing the same, a method of manufacturing a vertical MISFET and a vertical MISFET, and a method of manufacturing a semiconductor device and a semiconductor device
View Patent ↗Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.
1. A semiconductor device comprising:
memory cells including first MISFETs and second MISFETs;
a peripheral circuit including third MISFETs,
wherein the first MISFETs and the third MISFETs are formed on a major surface of a semiconductor substrate,
first interconnects formed over the first MISFETs and the third MISFETs with a first insulating film interposed therebetween,
wherein the first interconnects are comprised of a metal material; and
barrier metal layers formed over the first interconnects,
wherein the second MISFETs are formed over the barrier metal layers and electrically connected to the first MISFETs through the first interconnects and the barrier metal layers, and
wherein the third MISFETs are electrically connected to each other through the first interconnects.
2. A semiconductor device according to claim 1 ,
wherein each of the second MISFETs includes a source region, a channel forming region and a drain region each formed in a silicon film,
wherein each of the second MISFET includes a gate electrode formed on the silicon film through a gate insulating film,
wherein the first insulating film includes first openings,
wherein first plugs, each including a metal film, is formed in the first openings, and
wherein the silicon film is electrically connected to the first MISFET through the barrier metal layer, the first interconnect and the plug.
3. A semiconductor device according to claim 2 ,
wherein the barrier metal layer includes a titanium nitride (TiN) film, and
wherein the metal layer includes a tungsten (W) film.
4. A semiconductor device according to claim 1 ,
wherein the second MISFETs are vertical MISFETs.
5. A semiconductor device according to claim 1 ,
wherein memory cells of a static random memory include the first MISFETs and the second MISFETs serving as driver MISFETs and load MISFETs, respectively.
6. A semiconductor device according to claim 1 , further comprising;
a second insulating film formed over the second MISFET, the first interconnects, the barrier layers and the first insulating film,
the second insulating film including second openings, second plugs each including a metal film formed in the second openings; and
second interconnections formed over second insulating film, and electrically connected to the first interconnects through the second plugs.
7. A semiconductor device according to claim 1 ,
wherein the first MISFETs and the second MISFETs comprise memory cells,
wherein the third MISFETs comprises a peripheral circuit.