IP Library Patent Application 12379362
Patent Application
App. No. 12/379,362

Display device

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Quick Facts
Patent No.
US None
App. No.
12/379,362
Abstract

A display device is provided comprising a plurality of pixels disposed in a matrix form in a display area of a substrate, each of the plurality of pixels having a memory which stores written data, a scan line which is provided common to pixels arranged along a row direction and through which a scan signal is supplied to the pixels, and an image line which is provided common to pixels arranged along a column direction and through which an image signal is supplied to the pixels, wherein the scan signal is supplied to the scan line through a vertical address circuit or a vertical shift register circuit, and data is supplied to the image line through a horizontal scan shift register circuit.

Claims (11)

1 . A display device comprising:

a plurality of pixels disposed in a matrix form in a display area of a substrate, each of the plurality of pixels having a memory which stores written data;

a scan line which is provided common to pixels arranged along a row direction and through which a scan signal is supplied to the pixels; and

an image line which is provided common to pixels arranged along a column direction and through which an image signal is supplied to the pixels, wherein

the scan signal is supplied to the scan line through a vertical address circuit or a vertical shift register circuit, and

data is supplied to the image line through a horizontal scan shift register circuit.

2 . The display device according to claim 1 , wherein

the vertical address circuit and the horizontal scan shift register circuit are directly scanned by a signal from a CPU which is provided outside of the display device or indirectly scanned by a register in the display device.

3 . The display device according to claim 1 , further comprising:

an interface circuit which controls the vertical address circuit or the vertical shift register circuit and the horizontal scan shift register circuit, wherein

a CPU interface signal is used as an input signal for the interface circuit.

Assignments (3)
MERGER Recorded Dec 13, 2011
From: IPS ALPHA SUPPORT CO., LTD.
To: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
Reel/Frame 027482/0140 →
ATTACHED ARE (1) THE COMPANY SPLIT DOCUMENTS IN JAPANESE WITH ENGLISH TRANSLATION THEREOF AND (2) THE CERTIFICATE OF COMPANY SPLIT DOCUMENT IN JAPANESE WITH ENGLISH TRANSLATION, WHICH TOGETHER CONVEY 50% OWNERSHIP OF THE REGISTERED PATENTS AS LISTED IN THE ATTACHED TO EACH OF THE RECEIVING PARTIES (SEE PAGE 10, EXHIBIT 2-1, SECTION 1 OF THE ENGLISH TRANSLATION OF THE COMPANY SPLIT PLAN.) Recorded Dec 13, 2011
From: HITACHI, DISPLAYS, LTD.
To: HITACHI DISPLAYS, LTD.; IPS ALPHA SUPPORT CO., LTD.
Reel/Frame 027615/0589 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 19, 2009
From: YASUDA, KOZO
To: HITACHI DISPLAYS, LTD.
Reel/Frame 022325/0208 →