IP Library Granted Patent US 8,531,375
Granted Patent B2
US 8,531,375 · App. 12/379,406 · Granted Sep 10, 2013

Display device

Inventor: Fumiaki Komori (Isumi, JP)
Assignees: Hitachi Displays, Ltd.; Panasonic Liquid Crystal Display Co., Ltd.
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Quick Facts
Patent No.
US 8,531,375
App. No.
12/379,406
Granted
Sep 10, 2013
Kind
B2
Abstract

A display device includes a display panel, a control circuit and a random number generating circuit. The random number generating circuit includes a plurality of shift registers, an output circuit, and registers which holds initial values. By providing a plurality of initial values, the randomness of random numbers can be enhanced. Further, the random numbers different from each other can be outputted from the plurality of shift registers and hence, it is possible to increase the frequency and to output the increased frequency by an output circuit. Further, by adding a noise control signal which suppresses the number of inversion of a digital signal, electromagnetic wave noises generated from a liquid crystal display device can be reduced. Further, by adopting an intermittent drive clock which intermittently repeats stopping thereof as a basic clock of the plurality of shift registers, electromagnetic wave noises generated from the display device can be reduced. The basic clock may be a clock which is in synchronism with a transmission clock of the display data or a clock which is in asynchronism with a transmission clock of the display data.

Claims (33)

1. A display device comprising:

a display panel;

a drive circuit driving respective pixels of the display panel; and

a control circuit supplying display data to the drive circuit,

wherein the control circuit includes a random number generating circuit, the random number generating circuit includes an output circuit which increases a frequency of a pulse signal generated by the random number generating circuit n times, where n is an integer greater than one, and outputs a pulse signal of n-times increased frequency, the random number generating circuit includes n pieces of shift registers, a basic clock for n pieces of shift registers is an intermittent drive clock which intermittently alternates between a clock stopping period during which the random number generating circuit stops generating a random number and a clock outputting period, the basic clock being configured to controllably adjust an intermittent period thereof so as to control a level of radio waves generated by the random number generating circuit, and the control circuit outputs an inversion control signal indicative of inversion of the display data.

2. A display device according to claim 1 , wherein the basic clock is a clock which is in synchronism with a transmission clock of the display data.

3. A display device according to claim 1 , wherein the basic clock is a clock which is in asynchronism with a transmission clock of the display data.

4. A display device according to claim 1 , wherein the random number generating circuit includes a register which stores n pieces of initial values.

5. A display device comprising:

a display panel;

a drive circuit which drives respective pixels of the display panel;

a control circuit which outputs display data to the drive circuit;

a random number generating circuit which is provided to the control circuit;

a memory element which stores initial values of the random number generating circuit; and

an electromagnetic wave noise generating circuit into which signals generated by the random number generating circuit are inputted,

wherein the random number generating circuit includes n pieces of shift registers (where n is an integer greater than one), a basic clock of n pieces of shift registers is an intermittent drive clock which intermittently alternates between a clock stopping period during which the random number generating circuit stops generating a random number and a clock outputting period, the basic clock being configured to controllably adjust an intermittent period thereof so as to control a level of radio waves generated by the random number generating circuit, and the control circuit outputs an inversion control signal indicative of inversion of the display data.

6. A display device according to claim 5 , wherein the basic clock is a clock which is in synchronism with a transmission clock of the display data.

7. A display device according to claim 5 , wherein the basic clock is a clock which is in asynchronism with a transmission clock of the display data.

8. A display device according to claim 5 , wherein the random number generating circuit includes a register which stores n pieces of initial values.

9. A display device according to claim 5 , wherein the random number generating circuit includes an output circuit which is connected to n pieces of shift registers.

10. A display device comprising:

a display panel;

a touch panel which overlaps with the display panel in plane;

a drive circuit which drives respective pixels of the display panel;

a control circuit which outputs display data to the drive circuit;

a random number generating circuit which is provided to the control circuit;

a memory element which stores initial values of the random number generating circuit; and

an electromagnetic wave noise generating circuit into which signals generated by the random number generating circuit are inputted,

wherein the random number generating circuit includes n pieces of shift registers (where n is an integer greater than one), a basic clock of n pieces of shift registers is an intermittent drive clock which intermittently alternates between a clock stopping period during which the random number generating circuit stops generating a random number and a clock outputting period, the an electromagnetic wave noise circuit changes frequency of signals generated by the random number generating circuit, the basic clock being configured to controllably adjust an intermittent period thereof so as to control a level of radio waves generated by the random number generating circuit, and the control circuit outputs a noise control signal and controls the number of inversion of the display data.

11. A display device according to claim 10 , wherein the basic clock is a clock which is in synchronism with a transmission clock of the display data.

12. A display device according to claim 10 , wherein the basic clock is a clock which is in asynchronism with a transmission clock of the display data.

13. A display device according to claim 10 , wherein the random number generating circuit includes a register which stores n pieces of initial values.

14. A display device according to claim 10 , wherein the random number generating circuit includes an output circuit which is connected to n pieces of shift registers.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 10, 2025
From: JAPAN DISPLAY INC
To: MAGNOLIA PURPLE CORPORATION
Reel/Frame 071890/0202 →
CHANGE OF NAME Recorded Nov 17, 2023
From: HITACHI DISPLAYS, LTD.
To: JAPAN DISPLAY EAST, INC.
Reel/Frame 065614/0223 →
CHANGE OF NAME Recorded Nov 17, 2023
From: JAPAN DISPLAY EAST, INC.
To: JAPAN DISPLAY, INC.
Reel/Frame 065614/0644 →
CHANGE OF ADDRESS Recorded Nov 17, 2023
From: JAPAN DISPLAY, INC.
To: JAPAN DISPLAY, INC.
Reel/Frame 065654/0250 →
NUNC PRO TUNC ASSIGNMENT Recorded Nov 17, 2023
From: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
To: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
Reel/Frame 065615/0327 →
MERGER Recorded Dec 13, 2011
From: IPS ALPHA SUPPORT CO., LTD.
To: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
Reel/Frame 027482/0140 →
ATTACHED ARE (1) THE COMPANY SPLIT DOCUMENTS IN JAPANESE WITH ENGLISH TRANSLATION THEREOF AND (2) THE CERTIFICATE OF COMPANY SPLIT DOCUMENT IN JAPANESE WITH ENGLISH TRANSLATION, WHICH TOGETHER CONVEY 50% OWNERSHIP OF THE REGISTERED PATENTS AS LISTED IN THE ATTACHED TO EACH OF THE RECEIVING PARTIES (SEE PAGE 10, EXHIBIT 2-1, SECTION 1 OF THE ENGLISH TRANSLATION OF THE COMPANY SPLIT PLAN.) Recorded Dec 13, 2011
From: HITACHI, DISPLAYS, LTD.
To: HITACHI DISPLAYS, LTD.; IPS ALPHA SUPPORT CO., LTD.
Reel/Frame 027615/0589 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 20, 2009
From: KOMORI, FUMIAKI
To: HITACHI DISPLAYS, LTD.
Reel/Frame 022322/0952 →
Priority Claims (1)
JP 2008-082952 · Mar 27, 2008 · national
Continuity (1)
Related Publication 20090243990A1 · Oct 1, 2009