Interpolation accuracy improvement in motion encoder systems, devices and methods
View Patent ↗Disclosed are various embodiments of interpolation circuits for use in conjunction with motion encoders. The analog output signals provided by incremental or absolute motion encoders are provided to an interpolation circuit, which is capable of providing high interpolation factor output signals having high timing accuracy. Problems with noise spikes common to zero-hysteresis comparators typically employed in interpolation circuits are eliminated, as are problems with time delays differing between comparators that do feature hysteresis. The disclosed interpolation circuits may be implemented using CMOS processes without undue effort.
1. A method of interpolating sine and cosine analog signals generated by a motion encoder, the first and second analog signals each having a first frequency, comprising:
providing the sine and cosine signals as inputs to an interpolation processing circuit comprising first and second resistor strings configured to scale, respectively, the first and second analog signals before further processing by a plurality of comparators, each comparator being configured to generate a corresponding output pulse having a rising or falling edge timed to correspond to a predetermined one of a plurality of cross points of the scaled sine and cosine signals;
processing the sine and cosine signals in output circuitry of the interpolation processing circuit to yield a plurality of combined interpolated output signals which have a second frequency that is an integer multiple of the first frequency.
2. The method of claim 1 , wherein the sine signals comprise sine+ and sine− signals.
3. The method of claim 1 , wherein the cosine signals comprise cosine+ and cosine− signals.
4. The method of claim 1 , wherein the plurality of interpolated output signals comprises digital pulses having logic high levels separated by logic low levels.
5. The method of claim 1 , wherein the output circuitry further comprises a plurality of XOR gates located at outputs thereof, each XOR gate being configured to generate a corresponding interpolated output signal.
6. The method of claim 5 , wherein the output of each XOR gate is routed to through low-pass filter.
7. The method of claim 6 , wherein each low-pass filter is configured to filter out undesired noise spikes in its corresponding interpolated output signal.
8. The method of claim 7 , wherein the comparators of the interpolation processing circuit are zero hysteresis comparators.
9. The method of claim 1 , wherein each of the comparators has a predetermined custom hysteresis value associated therewith such that the delays caused by the comparators are substantially the same.
10. The method of claim 1 , wherein the second frequency ranges between two and twenty times the first frequency.
11. The method of claim 1 , wherein the interpolation processing circuit is fabricated using a CMOS process.
12. An interpolation processing circuit configured to receive sine and cosine analog signals generated by a motion encoder, the first and second analog signals each having a first frequency, comprising:
first and second resistor strings configured to scale, respectively, the first and second analog signals, and to provide scaled analog output signals therefrom;
a plurality of comparators configured to receive the scaled analog output signals, each comparator being configured to generate a corresponding output pulse having a rising or falling edge timed to correspond to a predetermined one of a plurality of cross points of the scaled sine and cosine signals; and
output circuitry disposed in the interpolation processing circuit and configured to receive the outputs provided by the plurality of comparators and process same to yield a plurality of combined interpolated output signals which have a second frequency that is an integer multiple of the first frequency.
13. The circuit of claim 12 , wherein the sine signals comprise sine+ and sine− signals.
14. The circuit of claim 12 , wherein the cosine signals comprise cosine+ and cosine− signals.
15. The circuit of claim 12 , wherein the plurality of interpolated output signals comprises digital pulses having logic high levels separated by logic low levels.
16. The circuit of claim 12 , wherein the output circuitry further comprises a plurality of XOR gates located at outputs thereof, each XOR gate being configured to generate a corresponding interpolated output signal.
17. The circuit of claim 16 , wherein the output of each XOR gate is routed to through low-pass filter.
18. The circuit of claim 17 , wherein each low-pass filter is configured to filter out undesired noise spikes in its corresponding interpolated output signal.
19. The circuit of claim 18 , wherein the comparators of the interpolation processing circuit are zero hysteresis comparators.
20. The circuit of claim 12 , wherein each of the comparators has a predetermined custom hysteresis value associated therewith such that the delays caused by the comparators are substantially the same.
21. The circuit of claim 12 , wherein the second frequency ranges between two and twenty times the first frequency.
22. The circuit of claim 12 , wherein the interpolation processing circuit is fabricated using a CMOS process.