ESD protection using isolated diodes
View Patent ↗An electrostatic discharge (ESD) protection circuit ( 40 ) is coupled across input-output (I/O) pads ( 21 ) and common terminals ( 24 ) of a core circuit ( 22 ) to protect it from ESD events. The circuit ( 40 ) comprises, a unidirectional ESD clamp ( 23 ) and two or more floating diodes ( 42, 44 ) arranged in parallel opposed configuration in series with the ESD clamp ( 23 ), the combination coupled between the I/O pads ( 21 ) and the reference terminals ( 24 ). In a preferred arrangement, the two strings of opposed parallel coupled diodes ( 42, 44 ) are used with different numbers of diodes in each string. These diodes ( 42, 44 ) operate in forward conduction ( 43, 45 ), so the energy dissipated therein during an ESD event is much reduced compared to a reverse biased diode and they can have smaller area. Signal clipping at the I/O pad ( 21 ) is reduced, less power is dissipated and less chip area is utilized.
1. An electronic device having input/output (I/O) and common terminals, comprising:
a circuit core coupled between the I/O terminal and the common terminal;
at least one substantially asymmetric electro-static discharge (ESD) clamp having first and second terminals, wherein the first terminal is coupled to one of the I/O terminal or the common terminal; and
two opposed floating diode strings formed in a polycrystalline semiconductor, each of the diode strings having therein multiple diodes coupled in series, wherein the diode strings are parallel coupled to third and fourth terminals, wherein the third terminal is coupled to the second terminal of the ESD clamp and the fourth terminal is coupled to the other of the I/O terminal or the common terminal, and wherein a first diode string of the two opposed floating diode strings comprises a first plurality of diodes coupled in series, wherein a first diode of the first plurality of diodes includes a first region of a first conductivity type and a first doping density, a second region of the first conductivity type directly adjacent the first region and having a second doping density that is less than the first doping density, and a third region of a second conductivity type directly adjacent the second region, and wherein a second diode of the first plurality of diodes includes a fourth region of the first conductivity type directly adjacent the third region and having the first doping density, a fifth region of the first conductivity type directly adjacent the fourth region and having the second doping density, and a sixth region of the second conductivity type directly adjacent the fifth region, and wherein the third region of the first diode is electrically coupled with the fourth region of the second diode.
2. The device of claim 1 , wherein a first of the two opposed floating diode strings has therein N diodes and a second of the two opposed floating diode strings has therein M diodes, and N≧M.
3. The device of claim 1 , wherein a first of the two opposed floating diode strings has therein N diodes and a second of the two opposed floating diode strings has therein M diodes, and N≧M+1.
4. The device of claim 3 , wherein N≦12.
5. The device of claim 3 , wherein M≦6.
6. The device of claim 1 , wherein the polycrystalline semiconductor comprises silicon.
7. The device of claim 1 , further comprising a common substrate on or in which the circuit core and the electrostatic discharge clamp are formed, and on which the two opposed floating diode strings are formed.
8. The device of claim 7 , wherein the substrate is conductive and further comprising an insulating layer interposed between the two opposed floating diode strings and the conductive substrate.
9. The device of claim 1 , wherein at least one of the two opposed floating diode strings formed in the polycrystalline semiconductor layer, comprises, a sequence of N and P regions having an odd number of PN junctions.
10. The device of claim 9 , wherein the number of PN junctions is N+(N−1) where N is the number of diodes comprising the diode string.
11. An electronic element having an electrostatic discharge (ESD) protection circuit for minimizing clipping of signals presented between an input-output (I/O) terminal and a reference terminal of a core circuit intended to be protected from ESD events occurring between the I/O terminal and reference terminal, comprising:
an asymmetrical ESD protection device providing forward conduction for a first current direction and ESD clamping for a second, opposite, current direction; and
opposed parallel coupled strings of diodes serially coupled to the ESD protection device to form a combination, wherein a first of the opposed parallel coupled strings has N serially arranged diodes therein and provides forward conduction for the first current direction and a second of the opposed parallel coupled strings has M serially arranged diodes therein and provides forward conduction for the second, opposite, current direction, and the combination is coupled between the I/O and reference terminals, and wherein a first diode string of the opposed parallel coupled strings of diodes comprises a first plurality of diodes coupled in series, wherein a first diode of the first plurality of diodes includes a first region of a first conductivity type and a first doping density, a second region of the first conductivity type directly adjacent the first region and having a second doping density that is less than the first doping density, and a third region of a second conductivity type directly adjacent the second region, and wherein a second diode of the first plurality of diodes includes a fourth region of the first conductivity type directly adjacent the third region and having the first doping density, a fifth region of the first conductivity type directly adjacent the fourth region and having the second doping density, and a sixth region of the second conductivity type directly adjacent the fifth region, and wherein the third region of the first diode is electrically coupled with the fourth region of the second diode.
12. The electronic element of claim 11 , wherein N≧M.
13. The electronic element of claim 12 , wherein N≧M+1.
14. The electronic element of claim 11 , wherein the core circuit, the ESD device and the first and second diode strings are formed in or on a common substrate so that the diode strings are separated from the common substrate by an insulating region.
15. The electronic element of claim 11 , further comprising:
a substrate; and
a polycrystalline semiconductor (PSC) layer on a surface of the substrate, wherein
the N diodes are formed in a first portion of the PSC layer by localized doping of the PSC layer, wherein the PSC layer has therein N+(N−1) PN junctions of which (N−1) are shorted together, and wherein
the M diodes are formed in a second portion of the PSC layer by localized doping of the PSC layer, wherein the PSC layer has therein M+(M−1) PN junctions of which (M−1) are shorted together.
16. The electronic element of claim 15 , wherein the PSC layer has an initial doping concentration less than that of P and N regions subsequently provided by localized doping thereof to form the PN junctions.
17. The electronic element of claim 11 , wherein the first region comprises a P+ type region, the second region comprises a P− type region directly abutting the first region, and the third region comprises an N+ type region directly abutting the second region.
18. The electronic element of claim 11 , wherein the first region comprises an N+ type region, the second region comprises an N− type region directly abutting the first region, and the third region comprises a P+ type region directly abutting the second region.