Sigma-delta modulator with digitally filtered delay compensation
View Patent ↗Apparatus are provided for continuous-time sigma-delta modulators. The sigma-delta modulator comprises an input node for an input signal and a quantizer configured to convert an analog signal to a digital value. A main feedback arrangement is coupled to the quantizer and configured to delay the digital value by a first delay period and generate a main feedback signal by digitally filtering the first delayed value. A compensation feedback arrangement is coupled to the quantizer and configured to delay the digital value by a second delay period, wherein the second delay period is not influenced by the first delay period, and generate a compensation feedback signal by digitally filtering the second delayed value. A forward signal arrangement produces the analog signal based on the input signal, the main feedback signal, and the compensation feedback signal.
1. An analog-to-digital converter comprising:
an input node for receiving an input signal;
a quantizer configured to convert a first analog signal to a digital value with a first sampling frequency;
a forward signal arrangement coupled between the input node and the quantizer;
a first delay element coupled to the quantizer, the first delay element being configured to delay the digital value by a first delay period resulting in a first delayed value;
a first digital-to-analog conversion arrangement coupled between the first delay element and the forward signal arrangement, the first digital-to-analog conversion arrangement being configured to generate a first feedback signal by digitally filtering the first delayed value, the first digital-to-analog conversion arrangement being configured for a second sampling frequency, the second sampling frequency being less than the first sampling frequency;
a second delay element coupled to the quantizer, the second delay element being configured to delay the digital value by a second delay period resulting in a second delayed value; and
a second digital-to-analog conversion arrangement coupled between the second delay element and the forward signal arrangement, the second digital-to-analog conversion arrangement being configured to generate a second feedback signal by digitally filtering the second delayed value, wherein the forward signal arrangement produces the first analog signal based on the input signal, the first feedback signal, and the second feedback signal.
2. The analog-to-digital converter of claim 1 , wherein the first digital-to-analog conversion arrangement comprises a polyphase digital-to-analog conversion arrangement.
3. The analog-to-digital converter of claim 2 , wherein the polyphase digital-to-analog conversion arrangement comprises an integer number of digital-to-analog converters, such that the second sampling frequency is equal to the first sampling frequency divided by the integer number of digital-to-analog converters.
4. The analog-to-digital converter of claim 1 , wherein the first digital-to-analog conversion arrangement comprises a first finite impulse response filtering arrangement.
5. The analog-to-digital converter of claim 4 , wherein the first finite impulse response filtering arrangement comprises a fractional delay finite impulse response filtering arrangement.
6. The analog-to-digital converter of claim 4 , wherein the first finite impulse response filtering arrangement comprises a lowpass comb filter.
7. The analog-to-digital converter of claim 4 , wherein the second digital-to-analog conversion arrangement comprises a second finite impulse response filtering arrangement.
8. The analog-to-digital converter of claim 1 , wherein the quantizer comprises a multi-bit quantizer.
9. A sigma-delta modulator comprising:
an input node for receiving an input signal;
a quantizer configured to convert a first analog signal to a digital value with a first sampling frequency;
a main feedback arrangement coupled to the quantizer, the main feedback arrangement comprising a plurality of digital-to-analog converters configured for a second sampling frequency that is less than the first sampling frequency, the main feedback arrangement being configured to:
delay the digital value by a first delay period to obtain a first delayed value; and
generate a main feedback signal by digitally filtering the first delayed value;
a compensation feedback arrangement coupled to the quantizer, the compensation feedback arrangement being configured to:
delay the digital value by a second delay period to obtain a second delayed value; and
generate a compensation feedback signal by digitally filtering the second delayed value; and
a forward signal arrangement coupled between the input node and the quantizer, the forward signal arrangement being coupled to the main feedback arrangement and the compensation feedback arrangement, wherein the forward signal arrangement produces the first analog signal based on the input signal, the main feedback signal, and the compensation feedback signal.
10. The sigma-delta modulator of claim 9 , wherein the plurality of digital-to-analog converters comprise non-return-to-zero digital-to-analog converters.
11. The sigma-delta modulator of claim 9 , wherein the main feedback arrangement comprises a first finite impulse response filtering arrangement configured to generate the main feedback signal by digitally filtering the first delayed value.
12. The sigma-delta modulator of claim 11 , wherein the compensation feedback arrangement comprises a second finite impulse response filtering arrangement configured to generate the compensation feedback signal by digitally filtering the second delayed value.
13. The sigma-delta modulator of claim 9 , wherein the second delay period is not equal to the first delay period.
14. The sigma-delta modulator of claim 9 , wherein the main feedback arrangement is coupled to the input node and the compensation feedback arrangement is coupled to the forward signal arrangement at a summing junction, wherein an element of the forward signal arrangement is coupled between the input node and the summing junction.
15. A sigma-delta modulator comprising:
an input node for receiving an input signal;
a first integrator having a first input and a first output, the first input being coupled to the input node;
a quantizer having a quantizer input and a quantizer output, the quantizer input being coupled to the first output, wherein the quantizer is configured to convert a first analog signal at the quantizer input to a digital value at the quantizer output with a first sampling frequency;
a main feedback arrangement coupled to the quantizer output and the input node, the main feedback arrangement comprising a plurality of digital-to-analog converters configured for operation at a second sampling frequency that is less than the first sampling frequency, the main feedback arrangement being configured to:
delay the digital value by a first delay period to obtain a first delayed value; and
generate a main feedback signal at the input node by digitally filtering the first delayed value; and
a compensation feedback arrangement coupled to the quantizer output and the first input, the compensation feedback arrangement being configured to:
delay the digital value by a second delay period to obtain a second delayed value; and
generate a compensation feedback signal at the first input by digitally filtering the second delayed value.
16. The sigma-delta modulator of claim 15 , further comprising a second integrator coupled between the input node and the first integrator, the second integrator having a second input coupled to the input node and a second output coupled to the first input.
17. The sigma-delta modulator of claim 15 , wherein the main feedback arrangement comprises:
a first delay element coupled to the quantizer output, the first delay element being configured to delay the digital value by the first delay period resulting in the first delayed value, wherein the plurality of digital-to-analog converters are coupled between the first delay element and the input node, the plurality of digital-to-analog converters being configured to generate the main feedback signal based at least in part on the first delayed value.
18. The sigma-delta modulator of claim 17 , wherein the compensation feedback arrangement comprises:
a second delay element coupled to the quantizer output, the second delay element being configured to delay the digital value by a second delay period to obtain the second delayed value; and
a compensation digital-to-analog conversion arrangement configured to generate the compensation feedback signal at the first input by digitally filtering the second delayed value, the compensation digital-to-analog conversion arrangement including at least one digital-to-analog converter configured for operation at the first sampling frequency.
19. The sigma-delta modulator of claim 18 , wherein the second delay period and the first delay period are different.