PROGRAMMABLE POWER SOURCE USING ARRAY OF RESISTIVE SENSE MEMORY CELLS
Various embodiments of the present invention are generally directed to an apparatus comprising a programmable power source which uses an array of resistive sense memory cells, such as but not limited to STRAM or RRAM cells, to provide a controlled power bias to a load, such as but not limited to a micro-oscillator. In some embodiments, the programmable power source incorporates an array of serially connected resistive sense memory cells. A selectively controllable power level is applied by the programmable power source to a load in relation to a control input which selectively programs at least selected ones of the memory cells to a selected resistance state.
1 . A programmable power source comprising an array of serially connected resistive sense memory cells configurable to provide an output responsive to a control input that programs at least one of the memory cells to a resistive state.
2 . The apparatus of claim 1 , wherein the selectively controllable power level comprises an output voltage bias at a preselected voltage level.
3 . The apparatus of claim 1 , wherein the selectively controllable power level comprises an output current bias as a preselected current level.
4 . The apparatus of claim 1 , wherein the array of serially connected resistive sense memory cells comprises a first set of N cells in series with a second set of M cells, wherein the first set of N cells are connected in series with the load, and wherein the second set of M cells are connected in parallel with the load.
5 . The apparatus of claim 1 , wherein the array of serially connected resistive sense memory cells comprises N cells connected in series with the load.
6 . The apparatus of claim 5 , wherein the array of serially connected resistive sense memory cells further comprises a plurality of cells connected in parallel with each of said N cells.
7 . The apparatus of claim 1 , wherein each memory cell of said array is selectively programmable to at least a first state of relatively low resistance and selectively programmable to at least a second state of relatively high resistance.
8 . The apparatus of claim 7 , wherein the control input is supplied by a controller which concurrently programs at least a first cell of said array in said first state and at least a second cell in said array in said second state.
9 . The apparatus of claim 1 , wherein each memory cell of said array is characterized as a spin-torque transfer random access memory (STRAM) cell.
10 . The apparatus of claim 1 , wherein each memory cell of said array is characterized as a resistive random access memory (RRAM) cell.
11 . The apparatus of claim 1 , wherein the array of memory cells comprises a first array of N rows of P memory cells, and wherein the programmable power source further comprises a second array of M rows of Q cells coupled to the first array and selection circuitry coupled to the first and second arrays, wherein the selection circuitry selectively interconnects the first and second arrays to respectively provide a selected voltage bias responsive to a first selection input thereto, and wherein the selection circuitry selectively interconnects the first and second arrays to respectively provide a selected current bias responsive to a different, second selection input thereto.
12 . The apparatus of claim 1 , wherein the load comprises a micro-oscillator without outputs an oscillating signal having a frequency selected in relation to said selectively controllable power level.
13 . The apparatus of claim 1 , wherein the programmable power source is incorporated into a semiconductor memory device comprising a non-volatile memory array of resistive sense memory cells.
14 . An apparatus comprising a power source which is configured to output a selectively controllable power level in relation to a resistance state programming control input.
15 . The apparatus of claim 14 , wherein the first means comprises a programmable power source comprising an array of serially connected resistive sense memory cells, wherein the selectively controllable power level is applied by the programmable power source to the load in relation to said control input which selectively programs at least selected ones of the memory cells to a selected resistance state.
16 . The apparatus of claim 15 , wherein each memory cell of said array is alternately programmable to a first state of relatively low resistance and a second state of relatively high resistance.
17 . The apparatus of claim 16 , wherein the array of serially connected resistive sense memory cells comprises N cells connected in series with the load.
18 . The apparatus of claim 17 , wherein the array of serially connected resistive sense memory cells further comprises M cells connected in series with said M cells and connected in parallel with the load.
19 . The apparatus of claim 16 , wherein each memory cell of said array is characterized as a spin-torque transfer random access memory (STRAM) cell.
20 . The apparatus of claim 16 , wherein each memory cell of said array is characterized as a resistive random access memory (RRAM) cell.