ACCESS MANAGEMENT TECHNIQUE FOR STORAGE-EFFICIENT MAPPING BETWEEN IDENTIFIER DOMAINS
Access management techniques have been developed to specify and facilitate mappings between I/O and host domains in ways that are storage-efficient and which can provide flexibility in the form, granularity and/or extent of mappings, attributes and access controls coded relative to a particular I/O domain. Indeed, different identifier and/or operation translation models may be employed on a per logical device (or even a per sub-window) basis. In general, the flexibility and efficiency afforded using some embodiments of the present invention can be desirable, particularly as numbers of I/O domains increase, such as in the case of virtualization system implementations in which a multiplicity of logical I/O devices may be represented using underlying physical resources.
1 . A method of mapping identifiers from a plurality of device-specific input/output (I/O) domains to respective identifiers in a host domain, the method comprising:
maintaining in storage accessible to an input/output (I/O) memory management unit a set of first-level table entries each coding access information for a respective logical device and corresponding to at least a portion of an I/O domain associated therewith, wherein the I/O domains associated with at least some of the logical devices are further decomposed into a plurality of subwindows;
maintaining in the accessible storage a set of second-level table entries each coding access information corresponding to respective ones of the subwindows, if any, for a particular I/O domain, wherein those of the second-level table entries, if any, corresponding to a particular I/O domain, code access information for less than all subwindows thereof;
mapping identifiers corresponding to a first subwindow of a first, device-specific I/O domain using a first one of the first-level table entries;
mapping identifiers corresponding to at least some remaining subwindows of the first, device-specific I/O domain using respective second-level table entries identifiable via the first, first-level table entry; and
mapping identifiers corresponding to at least a portion of a second, device-specific I/O domain using a second one of the first-level table entries.
2 . The method of claim 1 ,
wherein, in addition to the access information coded therein, the first- and second-level table entries code for each associated subwindow an address translation mode.
3 . The method of claim 2 ,
wherein the mapping of identifiers corresponding to one subwindow of the first device-specific I/O domain is in accordance with a window-based address translation mode; and
wherein the mapping of identifiers corresponding to another subwindow of the first device-specific I/O domain is in accordance with a page-based address translation mode.
4 . The method of claim 1 ,
wherein for respective ones of the device-specific I/O domains, the mappings of identifiers are in accordance with respective address translation modes coded therefor, and
wherein the address translation modes coded for at least one subwindow of the first device-specific I/O domains and for at least one subwindow of a third device-specific I/O domain differ.
5 . The method of claim 4 , wherein the differing address translation modes are individually selected from a set of modes that includes:
a window-based translation mode; and
a page-based translation mode.
6 . The method of claim 4 , wherein the differing address translation modes are individually selected from a set of modes that includes:
a no translation mode;
a page address translation mode;
a window-only address translation mode; and
a mode in which some addresses of a particular device-specific I/O domain are translated in accord with a page translation technique and other addresses within the particular device-specific I/O domain are translated in accord with a window translation technique.
7 . The method of claim 1 ,
wherein identifiers corresponding to respective subwindows of the second, device-specific I/O domain map to discontiguous portions of the host domain in accordance with mappings coded in respective ones of the first- and second-level table entries, and
wherein the mapping of identifiers corresponding to the second, device-specific I/O domain is to a contiguous portion of the host domain in accordance with mappings coded in the second first-level table entry.
8 . The method of claim 1 ,
wherein the second first-level table entry maps the entirety of the second, device-specific I/O domain.
9 . The method of claim 1 , wherein the second first-level table entry maps identifiers corresponding to a first subwindow of the second, device-specific I/O domain, the method further comprising:
mapping identifiers corresponding to at least some remaining subwindows of the second, device-specific I/O domain using respective second-level table entries identifiable via the second, first-level table entry.
10 . The method of claim 9 ,
wherein sub-windows of the first and second device-specific I/O domains are defined at differing granularities.
11 . The method of claim 1 ,
wherein the table entries for first and second device-specific I/O domains code different window extents.
12 . The method of claim 1 ,
wherein at least a portion of the first and the second device-specific I/O domains map via respective but distinct table entries to a same portion of the host domain.
13 . The method of claim 1 ,
wherein the table entries code both I/O to host domain mappings and host to I/O domain mappings.
14 . A method of managing mappings between a plurality of device-specific input/output (I/O) domains and a coherency domain, the method comprising:
instantiating in storage accessible to an I/O memory management unit a mapping data structure that defines for at least some of the device-specific I/O domains two-levels of mapping table entries; and
individually varying granularity of mappings for each of the device-specific I/O domains by coding in an associated first-level table entry of the mapping data structure whether and, if so, how many, subwindows are coded for the associated device-specific I/O domain.
15 . The method of claim 14 , further comprising:
for a particular device-specific I/O domain, coding mapping information for a first of the subwindows in the associated first-level table entry and coding mapping information for remaining ones of the subwindows in respective second-level table entries identifiable via the associated first-level table entry.
16 . The method of claim 14 , further comprising:
for at least some of the device-specific I/O domains, defining only a first-level table entry of the mapping data structure.
17 . The method of claim 14 , further comprising:
individually varying a mapped extent for respective device-specific I/O domains by coding a window size in the respective first-level table entry of the mapping data structure.
18 . The method of claim 14 , further comprising:
for a first of the device-specific I/O domains for which two-levels of mapping table entries are defined, defining a first subwindow size; and
for a second of the device-specific I/O domains for which two-levels of mapping table entries are defined, defining a second subwindow size, the second subwindow size differing from the first.
19 . An apparatus comprising:
a peripheral access management unit for coupling between storage and I/O resources to map from a plurality of logical device-specific I/O domains to respective locations in a coherent memory domain,
the peripheral access management unit configured to manage I/O accesses using a set of first-level table entries each coding access and address mapping information for a respective logical device and corresponding to at least a portion of an I/O domain associated therewith,
wherein I/O domains associated with at least some of the logical devices are further decomposed into a plurality of subwindows, the peripheral access management unit further configured to manage I/O accesses for a particular one of the further decomposed I/O domains using:
for a primary subwindow thereof, the corresponding first-level table entry; and
for respective secondary subwindows thereof, a set of second-level table entries each coding access information and address mapping for a respective one of the secondary subwindows.
20 . The apparatus of claim 19 , further comprising:
storage for the first- and second-level table entries, the storage accessible to the peripheral access management unit,
wherein at least one of the I/O domains is decomposed at a different subwindow granularity than another, and
wherein respective table entries code, for identifiers within respective subwindows of associated I/O domains, different address translation modes selected from an available set thereof that includes at least one window-based address translation mode and at least one page-based address translation mode.