Single transistor memory cell with reduced recombination rates
View Patent ↗A semiconductor fabrication method includes forming a semiconductor structure including source/drain regions disposed on either side of a channel body wherein the source/drain regions include a first semiconductor material and wherein the channel body includes a migration barrier of a second semiconductor material. A gate dielectric overlies the semiconductor structure and a gate module overlies the gate dielectric. An offset in the majority carrier potential energy level between the first and second semiconductor materials creates a potential well for majority carriers in the channel body. The migration barrier may be a layer of the second semiconductor material over a first layer of the first semiconductor material and under a capping layer of the first semiconductor material. In a one dimensional migration barrier, the migration barrier extends laterally through the source/drain regions while, in a two dimensional barrier, the barrier terminates laterally at boundaries defined by the gate module.
1. A transistor, comprising:
a first semiconductor material;
a buried dielectric material overlying the first semiconductor material;
a second semiconductor material overlying the buried dielectric material, wherein the second semiconductor material is electrically isolated from the first semiconductor material by the buried dielectric material and wherein the second semiconductor material is capable of storing a charge that represents a state of a memory device;
a gate electrode in contact with a gate dielectric;
wherein the second semiconductor material includes source/drain regions; and
a channel body intermediate between the source/drain regions and including a surface adjacent the gate dielectric wherein the channel body includes a majority carrier migration barrier of a third semiconductor material overlying the second semiconductor material, and wherein the migration barrier limits migration of majority carriers in the channel body to the surface of the channel body.
2. The transistor of claim 1 , wherein the migration barrier further limits migration of majority carriers in the channel body from migrating to the source/drain regions.
3. The transistor of claim 1 , wherein the presence of the migration barrier in the channel body creates an energy band offset between the first and second semiconductor materials.
4. The transistor of claim 1 , further comprising a capping layer of the first semiconductor located between the migration barrier and the gate dielectric.
5. The transistor of claim 4 , wherein the source/drain regions are n-type regions and the body portion is a p-type region and further wherein the first semiconductor material is silicon and the second semiconductor material is silicon germanium.
6. The transistor of claim 5 , wherein a germanium concentration of the silicon germanium is in the range of approximately 15 to 50%.
7. The transistor of claim 1 , wherein the source/drain regions and the channel body comprise a fin overlying a buried oxide layer and wherein conductive spacers formed adjacent sidewalls of the gate electrode serve as the gate electrode.
8. The transistor of claim 1 , wherein the migration barrier comprises a layer of the second semiconductor displaced below the gate electrode.
9. The transistor of claim 8 , wherein the migration barrier extends laterally into the source/drain regions.
10. The transistor of claim 8 , wherein the migration barrier terminates laterally at the source/drain extension regions.