Power estimation method and device therefor
View Patent ↗A set of instructions executable at an integrated circuit is partitioned into multiple instruction blocks. A first and second instruction block are executed multiple times, including a first execution and a second execution. The first execution of the first instruction block is associated with a first set of executions, and the first execution of the second instruction block is associated with a second set of executions. A first amount of energy consumption representative of a member of the first set of executions is determined, and a second amount of energy consumption representative of a member of the second set of executions is determined. The first amount of energy is assigned to each member of the first set, and the second amount of energy is assigned to each member of the second set, and used to determine a total amount of energy consumption associated with execution of the set of instructions.
1. A method comprising:
partitioning a set of instructions executable at an integrated circuit into a plurality of instruction blocks, wherein each instruction of the set of instructions is a member of exactly one instruction block, each instruction block includes at least two instructions, and the last instruction included at each instruction block is a non-sequential instruction;
simulating, at a computer, execution of the set of instructions at a first software representation of the integrated circuit, wherein during execution of the set of instructions a first instruction block is executed a plurality of times, including a corresponding first execution and second execution, and a second instruction block is executed a plurality of times including a corresponding first execution and second execution, the simulating further to determine a value representing a record of a state of design attributes of the integrated circuit during each execution;
associating the first execution of the first instruction block with a first set of executions based on the determined value;
associating the second execution of the first instruction block with a second set of executions based on the determined value;
determining, using a second software representation of the integrated circuit, a first amount of energy consumption that is representative of a member of the first set of executions;
determining, using the second software representation, a second amount of energy consumption that is representative of a member of the second set of executions;
assigning the first amount of energy consumption to each member of the first set of executions;
assigning the second amount of energy consumption to each member of the second set of executions; and
determining a total amount of energy consumption associated with execution of the set of instructions, the total amount of energy consumption based on energy consumed by a plurality of sets of executions including the first set and the second set of executions, wherein each member of the first set of executions contributes the assigned first amount of energy consumption to the total amount of energy consumption, and each member of the second set of executions contributes the assigned second amount of energy consumption to the total amount of energy consumption.
2. The method of claim 1 further comprising:
associating the first execution of the second instruction block with a third set of executions based on the determined value.
3. The method of claim 1 further comprising:
associating the second execution of the second instruction block with a third set of executions based on the determined value.
4. The method of claim 2 , further comprising associating all executions of the second instruction block with the third set of executions based on the determined value.
5. The method of claim 1 ,
wherein associating the first execution of the first instruction block with the first set of executions is based on the determined value stored at a register included at the first design representation of the integrated circuit.
6. The method of claim 5 further comprising:
associating the first execution of the first instruction block with the first set of executions in response to a first bit of the register having a first logic value, and associating the second execution of the first instruction block with the second set of executions in response to the first bit having a second logic value.
7. The method of claim 1 , wherein
associating the first execution of the first instruction block with the first set of executions is based on the determined value stored at a cache memory.
8. The method of claim 1 , wherein
associating the first execution of the first instruction block with the first set of executions is based on the determined value stored at a memory stack.
9. The method of claim 1 , wherein
partitioning further comprises partitioning each instruction block of the plurality of instructions blocks include only one non-sequential instruction.
10. The method of claim 1 , wherein
determining the first amount of energy consumption that is representative of the member of the first set of executions includes simulating the operation of the first execution of the first instruction block, wherein the energy consumption that is representative of the member of the first set of executions is based on the simulation of the first execution of the first instruction block.
11. The method of claim 10 , wherein
an energy consumption that is representative of the member of the first set of executions is based only upon the simulation of the first execution of the first instruction block.
12. The method of claim 10 , wherein
the first software representation includes a register-transfer-level representation of the integrated circuit and the second software representation includes a gate level or transistor level representation of the integrated circuit.
13. A device comprising:
a memory;
a partition module coupled to the memory to receive a set of instructions executable at an integrated circuit, and to partition the set of instruction into a plurality of instruction blocks, wherein each instruction of the set of instructions is a member of exactly one instruction block, each instruction block includes at least two instructions, and the last instruction included at each instruction block is a non-sequential instruction;
a simulation module coupled to the memory and to the partition module to simulate execution of the set of instructions at a first software representation of the integrated circuit, wherein during execution of the set of instructions a first instruction block is to be executed a plurality of times, including a corresponding first execution and second execution, and a second instruction block is to be executed a plurality of times, including a corresponding first execution and second execution, the simulating further to determine a value representing a record of a state of design attributes of the integrated circuit during each execution;
a classification module coupled to the memory and to the simulation module to associate the first execution of the first instruction block with a first set of executions, and to associate the second execution of the first instruction block with a second set of executions, the associating based on the determined value;
an energy characterization module coupled to the memory and to the classification module to determine a first amount of energy consumption that is representative of a member of the first set of executions, and to determine a second amount of energy consumption representative of a member of the second set of executions, the energy characterization module to simulate operation of a second software representation of the integrated circuit;
an assignment module coupled to the memory and to the energy characterization module to assign the first amount of energy consumption to each member of the first set of executions, and to assign the second amount of energy consumption to each member of the second set of executions; and
an analysis module coupled to the memory and to the assignment module to determine a total amount of energy consumption associated with execution of the set of instructions, the total amount of energy consumption based on energy consumed by a plurality of sets of executions including the first set and the second set of executions, wherein each member of the first set of executions contributes the assigned first amount of energy consumption to the total amount of energy consumption, and each member of the second set of executions contributes the assigned second amount of energy consumption to the total amount of energy consumption.
14. The device of claim 13 wherein the classification module is to further associate the first execution of the second instruction block with a third set of executions based on the determined value.
15. The device of claim 13 , wherein:
the classification module is to further associate the first execution of the second instruction block with a third set of executions;
the energy characterization module is to further determine a third amount of energy consumption representative of a member of the third set of executions;
the assignment module is to further assign the third amount of energy consumption to each member of the third set of executions; and
the analysis module wherein each member of the third set of executions contributes the third amount of energy consumption to the total amount of energy consumption.
16. A non-transitory computer readable medium embodying a software program, the software program comprising executable instructions configured to manipulate at least one processor to:
partition a set of instructions executable at an integrated circuit into a plurality of instruction blocks, wherein each instruction of the set of instructions is a member of exactly one instruction block, each instruction block includes at least two instructions, and the last instruction included at each instruction block is a non-sequential instruction;
simulate execution of the set of instructions at a first software representation of the integrated circuit, wherein during execution of the set of instructions a first instruction block of the plurality of instruction blocks is executed a plurality of times, including a corresponding first execution and second execution, and a second instruction block of the plurality of instruction blocks is executed a plurality of times, including a corresponding first execution and second execution, the simulating further to determine a value representing a record of a state of design attributes of the integrated circuit during each execution;
associate the first execution of the first instruction block with a first set of executions based on the determined value;
associate the first execution of the second instruction block with a second set of executions based on the determined value;
determine, using a second software representation of the integrated circuit a first amount of energy consumption that is representative of a member of the first set of executions;
determine, using the second software representation of the integrated circuit, a second amount of energy consumption that is representative of a member of the second set of executions;
assign the first amount of energy consumption to each member of the first set of executions;
assign the second amount of energy consumption to each member of the second set of executions; and
determine a total amount of energy consumption associated with execution of the set of instructions, the total amount of energy consumption based on energy consumed by a plurality of sets of executions including the first set and the second set of executions, wherein each member of the first set of executions contributes the assigned first amount of energy consumption to the total amount of energy consumption, and each member of the second set of executions contributes the assigned second amount of energy consumption to the total amount of energy consumption.
17. The computer readable medium of claim 16 , the software program is further configured to manipulate the at least one processor to:
associate the first execution of the first instruction block with the first set of executions based on the determined value stored at a register included at the first software representation of the integrated circuit.
18. The computer readable medium of claim 1 ,, wherein the software program is further configured to manipulate the at least one processor to:
associate the first execution of the first instruction block with the first set of executions in response to a first bit of the register having a first logic value, and associating the second execution of the first instruction block with the second set of executions in response to the first bit of the register having a second logic value.