IP Library Granted Patent US 7,969,179
Granted Patent B2
US 7,969,179 · App. 12/414,752 · Granted Jun 28, 2011

Method and apparatus for increasing security in a system using an integrated circuit

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Quick Facts
Patent No.
US 7,969,179
App. No.
12/414,752
Granted
Jun 28, 2011
Kind
B2
Abstract

An integrated circuit can be made more secure by programming a one time programmable circuit so that different signals are provided on terminals as compared to when the integrated circuit was not secure. Instead, or in addition, the integrated circuit can be made more secure by providing decode circuitry that can be used with the one time programmable circuit to select different internal address maps in response to an address value. The decode circuitry can use a first address map when the integrated circuit is secure, and a different address map when the integrated circuit is non-secure.

Claims (31)

1. A method, comprising:

providing a first integrated circuit having a first security feature; and

providing a second integrated circuit having a second security feature,

wherein the first integrated circuit and the second integrated circuit are formed comprising identical circuitry, and the first security feature is identical to the second security feature,

wherein the first integrated circuit and the second integrated circuit each has a plurality of external terminals and a first external terminal assignment of the plurality of external terminals,

wherein when the first security feature of the first integrated circuit is not enabled, the first integrated circuit comprises a non-secure integrated circuit having the first external terminal assignment,

wherein when the second security feature of the second integrated circuit is enabled, the second integrated circuit comprises a secure integrated circuit having a second external terminal assignment, the second external terminal assignment being different from the first external terminal assignment,

wherein the secure integrated circuit maps one of a chip select signal or a module to a first address value, and

wherein the non-secure integrated circuit maps one of said chip select signal or said module to a second address value that is different than the first address value, wherein the non-secure integrated circuit is incapable of mapping said chip select signal to the first address value, and wherein the non-secure integrated circuit is incapable of mapping said module to the first address value, and

wherein the second external terminal assignment of the secure integrated circuit is permanent and cannot be reversed.

2. A method as in claim 1 , wherein the second security feature of the second integrated circuit is enabled by programming a one time programmable circuit to a second value.

3. A method as in claim 2 , wherein when the first security feature of the first integrated circuit is not enabled, the one time programmable circuit is left unprogrammed and defaults to a first value, wherein the first value is different than the second value.

4. A method as in claim 2 , wherein the one time programmable circuit comprises an electrically programmable fuse.

5. A method as in claim 1 , wherein the first and second integrated circuit each comprise a debug circuit, wherein a first subset of the plurality of external terminals is assigned to the debug circuit when the first and second security features are not enabled, and a second subset of the plurality of external terminals is assigned to the debug circuit when the first and second security features are enabled, the second subset being different than the first subset.

6. A method as in claim 1 , wherein each one of the plurality of external terminals comprises a conductive bump.

7. A method as in claim 1 , wherein the enabling of the second security feature of the second integrated circuit is permanent and cannot be reversed.

8. A method, comprising:

providing a first integrated circuit having a first security feature; and

providing a second integrated circuit having a second security feature,

wherein the first integrated circuit and the second integrated circuit are formed comprising identical circuitry, and the first security feature is identical to the second security feature,

wherein when the first security feature of the first integrated circuit is not enabled, the first integrated circuit comprises a non-secure integrated circuit,

wherein when the second security feature of the second integrated circuit is enabled, the second integrated circuit comprises a secure integrated circuit,

wherein the secure integrated circuit maps one of a chip select signal or a module to a first address value, and

wherein the non-secure integrated circuit maps one of said chip select signal or said module to a second address value that is different than the first address value, wherein the non-secure integrated circuit is incapable of mapping said chip select signal to the first address value, and wherein the non-secure integrated circuit is incapable of mapping said module to the first address value.

9. A method as in claim 8 , wherein the second security feature of the second integrated circuit is enabled by programming a one time programmable circuit to a second value.

10. A method as in claim 9 , wherein when the first security feature of the first integrated circuit is not enabled, the one time programmable circuit is left unprogrammed and defaults to a first value, wherein the first value is different than the second value.

11. A method as in claim 9 , wherein the one time programmable circuit comprises an electrically programmable fuse.

12. A method as in claim 8 , wherein the first address value comprises a range of contiguous addresses.

13. A method as in claim 8 , wherein the chip select signal is transferred to a device located external to the secure integrated circuit.

14. A method as in claim 8 , wherein the module is located on the secure integrated circuit.

15. A method as in claim 8 , wherein the enabling of the second security feature of the second integrated circuit is permanent and cannot be reversed.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →