Integrated circuit having an embedded memory and method for testing the memory
View Patent ↗A memory system has a first memory having an array of memory cells that includes a redundant column. The redundant column substitutes for a first column in the array. The first column includes a test memory cell. The array receives a power supply voltage. The test memory cell becomes non-functional at a higher power supply voltage than the memory cells of the array. A memory controller is coupled to the first memory and is for determining if the test memory cell is functional at a first value for the power supply voltage. This is useful in making decisions concerning the value of the power supply voltage applied to the array.
1. A memory system, comprising:
a first memory having an array of memory cells includes a redundant column, wherein:
the redundant column substitutes for a first column in the array,
wherein the first column includes a test memory cell;
the array receives a power supply voltage, wherein the power supply voltage has a first value during a low power operating mode and the power supply voltage has a second value during a normal operating mode, the second value being higher than the first value; and
the test memory cell becomes non-functional at a higher power supply voltage than the memory cells of the array; and
a memory controller, coupled to the first memory, for determining if the test memory cell is functional at the first value for the power supply voltage during a read operation of the first memory to determine if the array of memory cells of the first memory have an adequate operating margin when the power supply voltage is lowered to the first value.
2. The memory system of claim 1 , further comprising a voltage regulation circuit for supplying the power supply voltage.
3. The memory system of claim 2 , further comprising a processor for selecting values of the power supply voltage for the voltage regulation circuit to provide to the array.
4. The memory system of claim 3 , wherein the processor selects the second value of the power supply voltage for the voltage regulation circuit if the memory controller determines that the test memory cell is not functional with the power supply voltage at the first value.
5. The memory system of claim 4 , wherein the processor selects a third value, which is less than the first value, of the power supply voltage for the voltage regulation circuit to supply to the array if the memory controller determines that the test memory cell is functional with the power supply voltage at the first value.
6. The memory system of claim 5 wherein, if the processor selects the third value, the memory controller determines if the test memory cell is functional at the third value for the power supply voltage.
7. The memory system of claim 6 wherein the processor selects a fourth value, which is less than the third value, of the power supply voltage for the voltage regulation circuit to supply to the array if the memory controller determines that the test memory cell is functional with the power supply voltage at the third value.
8. The memory system of claim 1 , wherein:
the test memory cell is more stable in a first logic state than a second logic state; and
the memory controller determines if the test memory cell is functional when the test memory cell is in the second logic state.
9. The memory system of claim 8 , wherein the memory controller determines if the test memory cell is functional when the test memory cell is in the first logic state.
10. The memory system of claim 1 , wherein:
the test memory cell is coupled to a word line;
a functional column is adjacent to the first column;
a functional memory cell in the functional column is coupled to the word line;
the memory controller writes data that is the same to the first column and the functional column; and
the memory controller determines if the test memory cell is functional by comparing a logic state of the functional memory cell to a logic state of the test memory cell.
11. The memory system of claim 1 , wherein:
the first memory comprises a plurality of sense amplifiers, wherein the first column is coupled to first sense amplifier of the plurality of sense amplifiers; and
a plurality of multiplexers, wherein each multiplexer is coupled to adjacent pairs of sense amplifiers of the plurality of sense amplifiers wherein each sense amplifier is coupled to two multiplexers of the plurality of multiplexers.
12. The memory system of claim 1 , further comprising a second memory having a second array of memory cells that includes a second redundant column, wherein:
the second redundant column substitutes for a second column in the second array,
wherein the second column includes a second test memory cell;
the second array receives the power supply voltage; and
the second test memory cell becomes non-functional at a higher power supply voltage than the memory cells of the second array; and
the memory controller, coupled to the second memory, is for determining if the second test memory cell is functional at a second value for the power supply voltage.