Granted Patent B2

US 8,315,117 · App. 12/414,761 · Granted Nov 20, 2012

Abstract

Claims (43)

1. A method comprising:

testing, using a first test, a plurality of static random access memory elements to determine a lowest power supply voltage at which all the plurality of memory elements will operate;

determining a weak memory element of the plurality of static random access memory elements;

substituting a portion of a plurality of redundant static random access memory elements for a portion of the plurality of static random access memory elements that includes the weak memory element;

designating the weak memory element to be a test element;

supplying the plurality of static random access memory elements with a first power supply voltage;

receiving a request for a change of the first power supply voltage to a second power supply voltage;

in response to receiving the request, testing, using a second test, the test element to determine if the test element will function correctly at the second power supply voltage,

if the test element passes the second test, accessing the plurality of static random access memory elements at the second power supply voltage, and

if the test element fails the second test, accessing the plurality of static random access memory elements using an access assist operation.

2. The method of claim 1 , wherein the weak memory element is one of either a memory cell, a plurality of memory cells, a row of memory cells, and a column of memory cells.

3. The method of claim 1 , wherein the access assist operation comprises one of either using the first power supply voltage during the accessing of the plurality of memory elements, accessing the plurality of memory elements using a predetermined power supply voltage determined using the first test, applying a negative voltage to a bit line during the accessing of the plurality of memory elements, and applying a third power supply voltage determined during a third test during the accessing of the plurality of memory elements.

4. The method of claim 3 wherein accessing the plurality of memory elements at the third power supply voltage further comprises providing the third power supply voltage for only for the duration of the access.

5. The method of claim 3 , wherein the first test is characterized as being a built-in self test, and the second and third tests are characterized as being performed during a functional operating mode of the plurality of memory elements.

6. The method of claim 1 , wherein substituting the portion of the plurality of redundant memory cells for the portion of the plurality of memory cells that includes the weak memory element further comprises substituting a column of the plurality of redundant memory elements for a column of the plurality memory elements that includes the weak memory element.

7. The method of claim 1 , wherein designating the weak memory element to be a test element further comprises using the test element only during the second test.

8. The method of claim 1 , further comprising supplying the plurality of memory elements with the second power supply voltage after the access is complete.

9. The method of claim 1 , wherein the plurality of memory elements are characterized as being part of an embedded memory in a single-chip data processing system.

10. A method for accessing a memory array comprising:

implementing redundancy in the memory array to substitute a redundant memory cell for a failed memory cell;

testing, using a first test, the memory array to determine a lowest power supply voltage at which all memory cells of the memory array will operate;

determining a weak memory cell of the memory array;

substituting a redundant memory cell for the weak memory cell;

designating the weak memory cell to be only a test cell;

supplying the memory array with a first power supply voltage;

receiving a request for a change of the first power supply voltage to a second power supply voltage;

in response to receiving the request, testing, using a second test, the test cell to determine if both read and write operations can be performed correctly on the test cell at the second power supply voltage,

if the test cell passes the second test, accessing the memory array at the second power supply voltage, and

if the test cell fails the second test, providing a third power supply voltage to the test cell and testing the test cell using a third test to determine if the test cell will function correctly at the third power supply voltage; and

if the test cell passes the third test, accessing the memory array at the third power supply voltage.

11. The method of claim 10 , wherein the second and third power supply voltages are generated on a same integrated circuit as the memory array.

12. The method of claim 10 , wherein substituting a redundant memory cell for the weak memory cell further comprises substituting a redundant column of memory cells for a column of memory cells having the weak memory cell.

13. The method of claim 10 , wherein the plurality of memory cells comprises a plurality of static random access memory cells.

14. The method of claim 10 wherein accessing the memory array at the third power supply voltage further comprises providing the third power supply voltage for only for the duration of the access.

15. The method of claim 10 , wherein the plurality of memory cells are characterized as being part of an embedded memory in a single-chip data processing system.

16. An integrated circuit comprising:

a memory array comprising a plurality of static random access memory cells organized in rows and columns, wherein a memory cell of the plurality of static random access memory cells is designated as a test memory cell;

a plurality of redundant static random access memory cells for implementing redundancy in the memory array, wherein a redundant memory cell of the plurality of redundant static random access memory cells is used to substitute for the test memory cell during operation of the integrated circuit;

an error detection circuit, coupled to the memory array, for detecting a failure of the test memory cell concurrently with an access to a memory cell of the plurality of static random access memory cells; and

a voltage control circuit, coupled to the memory array and to the error detection circuit, for activating an access assist operation in response to the error detection circuit detecting a failure of the test memory cell, wherein the access assist operation comprises one of either using a first power supply voltage during a write operation of the plurality of static random access memory elements at which the test memory cell functions correctly, applying a negative voltage to a bit line during the write operation of the plurality of static random access memory elements, and applying a second power supply voltage determined during a read operation of the plurality of static random access memory elements.

17. The integrated circuit of claim 16 , wherein the test memory cell is characterized as being a memory cell of the memory array that operates unreliably at a relatively high power supply voltage.

18. The integrated circuit of claim 16 , wherein the error detection circuit provides an access error signal to the voltage control circuit in response to detecting the failure of the test memory cell, and wherein the voltage control circuit changes one of either the power supply voltage to the memory array or a bit line voltage in response to the access error signal.

19. The integrated circuit of claim 16 , wherein the voltage control circuit comprises a comparator having a first input coupled to a first bit line, a second input coupled to a second bit line, and an output coupled to an input of the error detection circuit.

Assignments (18)