IP Library Granted Patent US 7,932,558
Granted Patent B2
US 7,932,558 · App. 12/424,119 · Granted Apr 26, 2011

Semiconductor device and method for manufacturing the same

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Quick Facts
Patent No.
US 7,932,558
App. No.
12/424,119
Granted
Apr 26, 2011
Kind
B2
Abstract

A semiconductor device includes: an n-type first well diffusion layer; an n-type second well diffusion layer; a p-type source diffusion layer; a p-type third well diffusion layer; a p-type drain diffusion layer; a gate insulating film; a gate electrode; a device isolation insulating film; and a buffer layer. The buffer layer is formed between the first well diffusion layer and the third well diffusion layer to be in contact with an end of the third well diffusion layer opposing the source diffusion layer, and extends from immediately below the gate insulating film to a position deeper than a peak of curvature of impurity concentration distribution of the third well diffusion layer. The buffer layer has an impurity concentration lower than an impurity concentration in the third well diffusion layer.

Claims (22)

1. A semiconductor device comprising:

a semiconductor substrate;

a first well diffusion layer of a first conductivity type formed in an upper portion of the semiconductor substrate;

a second well diffusion layer of the first conductivity type formed in an upper portion of the first well diffusion layer;

a source diffusion layer of a second conductivity type formed in an upper portion of the second well diffusion layer;

a third well diffusion layer of the second conductivity type formed in an upper portion of the semiconductor substrate to be positioned away from the second well diffusion layer, and forms a PN junction with the first well diffusion layer;

a drain diffusion layer of the second conductivity type formed in an upper portion of the third well diffusion layer;

a gate insulating film formed on the second well diffusion layer, the first well diffusion layer, and the third well diffusion layer;

a gate electrode formed on the gate insulating film;

a device isolation insulating film formed on the third well diffusion layer and between the gate insulating film and the drain diffusion layer to be connected to the gate insulating film; and

a buried diffusion layer of the first conductivity type formed in part of the semiconductor substrate in contact with the bottoms of both of the first well diffusion layer and the third well diffusion layer.

2. The semiconductor device of claim 1 , further comprising:

a surface diffusion layer of the second conductivity type formed in surface portions of the second well diffusion layer, the first well diffusion layer, the buffer layer and the third well diffusion layer immediately below the gate insulating film.

3. The semiconductor device of claim 1 , wherein

the first well diffusion layer is positioned closer to the source diffusion layer than the third well diffusion layer.

4. The semiconductor device of claim 1 , further comprising:

a buffer layer of the second conductivity type formed between the first well diffusion layer and the third diffusion layer to be in contact with an end of the third well diffusion layer opposing the source diffusion layer.

5. The semiconductor device of claim 4 , wherein

the buffer layer is made of the same material as the semiconductor substrate and contains an impurity of the second conductivity type at substantially the same concentration as the impurity concentration in the semiconductor substrate.

6. The semiconductor device of claim 4 , wherein

the buffer layer contains the impurity of the second conductivity type at a higher concentration than the impurity concentration in the semiconductor substrate.

7. The semiconductor device of claim 4 , wherein the buffer layer of the second conductivity type extends from immediately below the gate insulating film to a position deeper than a peak of curvature of impurity concentration distribution of the third well diffusion layer, and the buffer layer has an impurity concentration lower than an impurity concentration in the third well diffusion layer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 7, 2015
From: PANASONIC CORPORATION
To: PANNOVA SEMIC, LLC
Reel/Frame 036065/0273 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 15, 2009
From: KOBAYASHI, YASUSHI; IMAHASHI, MANABU
To: PANASONIC CORPORATION
Reel/Frame 022827/0743 →