Capacitive touch sensor system
View Patent ↗A method of matrix sensing using delay-based capacitance sensing, including using X-axis lines as active lines for capacitance measurements and using Y-axis lines as a disturbance to identify the location of a touch in a key matrix is disclosed. A sensing signal is applied to the X-axis lines, and a disturbance signal is applied to the Y-axis lines. If a location is touched, cross-capacitance is reduced, which is measured by sweeping data along the X-axis lines.
1. A time-to-digital converter comprising:
a first delay chain having an input for receiving a capture reference signal, and a final output; and
a second delay chain having a first input coupled to the final output of the first delay chain, a second input for receiving a measuring signal, and an output for providing a digital quantized value,
wherein an incremental delay of the first delay chain is greater than an incremental delay of the second delay chain.
2. The time-to-digital converter of claim 1 , wherein the first delay chain comprises a plurality of serially coupled delay stages.
3. The time-to-digital converter of claim 2 , wherein each delay stage comprises:
a delay element having an input coupled to an input of the delay stage, and an output; and
a multiplexer having a first input coupled to the input of the delay stage, a second input coupled to the output of the delay element, a control input for receiving a control signal, and an output coupled to the output of the delay stage.
4. The time-to-digital converter of claim 3 wherein the delay element comprises a buffer stage.
5. The time-to-digital converter of claim 3 wherein the delay element comprises an inverter.
6. The time-to-digital converter of claim 1 , wherein the second delay chain comprises a plurality of serially coupled delay stages.
7. The time-to-digital converter of claim 6 , wherein each delay stage comprises:
a D-type flip-flop having a clock input for receiving a clock signal, a D input, and an output for providing a digital quantized value; and
a delay element coupled to the D input of the D-type flip-flop.
8. The time-to-digital converter of claim 7 , wherein the delay element comprises a buffer stage.
9. The time-to-digital converter of claim 7 , wherein the delay element comprises an inverter.
10. The time-to-digital converter of claim 1 , wherein the incremental delay of the first delay chain is a predetermined percentage greater than the incremental delay of the second delay chain.
11. A touch pad or touch screen system comprising:
a plurality of X-axis lines used as active lines for capacitance measurements;
a plurality of Y-axis lines used as a disturbance to identify the location of a touch in a key matrix;
a capacitance-to-time converter coupled to the plurality of X-axis and Y-axis lines; and
a time-to-digital converter coupled to the capacitance-to-time converter, wherein the time-to-digital converter comprises a first delay chain having an input for receiving a capture reference signal, and a final output, and a second delay chain having a first input coupled to the final output of the first delay chain, a second input for receiving a measuring signal, and an output for providing a digital quantized value, wherein an incremental delay of the first delay chain is greater than an incremental delay of the second delay chain.
12. The system of claim 11 , wherein the first delay chain comprises a plurality of serially coupled delay stages.
13. The system of claim 12 , wherein each delay stage comprises:
a delay element having an input coupled to an input of the delay stage, and an output; and
a multiplexer having a first input coupled to the input of the delay stage, a second input coupled to the output of the delay element, a control input for receiving a control signal, and an output coupled to the output of the delay stage.
14. The system of claim 13 wherein the delay element comprises a buffer stage.
15. The system of claim 13 wherein the delay element comprises an inverter.
16. The system of claim 11 , wherein the second delay chain comprises a plurality of serially coupled delay stages.
17. The system of claim 16 , wherein each delay stage comprises:
a D-type flip-flop having a clock input for receiving a clock signal, a D input, and an output for providing a digital quantized value; and
a delay element coupled to the D input of the D-type flip-flop.
18. The system of claim 17 , wherein the delay element comprises a buffer stage.
19. The system of claim 17 , wherein the delay element comprises an inverter.
20. The system of claim 11 , wherein the incremental delay of the first delay chain is a predetermined percentage greater than the incremental delay of the second delay chain.
21. A time-to-digital converter comprising:
a reference delay chain having an input for receiving a capture reference signal, and a final output; and
a measurement delay chain having a first input coupled to the final output of the reference delay chain, a second input for receiving a measuring signal, and an output for providing a digital quantized value, wherein an incremental delay of the reference delay chain is greater than an incremental delay of the measurement delay chain.