Semiconductor device with strained transistors and its manufacture
View Patent ↗A semiconductor device has: a semiconductor substrate made of a first semiconductor material; an n-channel field effect transistor formed in the semiconductor substrate and having n-type source/drain regions made of a second semiconductor material different from the first semiconductor material; and a p-channel field effect transistor formed in the semiconductor substrate and having p-type source/drain regions made of a third semiconductor material different from the first semiconductor material, wherein the second and third semiconductor materials are different materials. The semiconductor device having n- and p-channel transistors has improved performance by utilizing stress.
1. A method of manufacturing a semiconductor device comprising:
(1) forming a first gate electrode above an n-channel field effect transistor region of a semiconductor substrate made of a first semiconductor material, and forming a second gate electrode above a p-channel field effect transistor region of the semiconductor substrate made of the first semiconductor material;
(2) forming a first insulating mask layer over the semiconductor substrate, covering the first gate electrode and the second gate electrode;
(3) forming a resist mask covering the p-channel field effect transistor region and exposing the n-channel field effect transistor region, anisotropically etching the first insulating mask layer in the n-channel field effect transistor region to leave the first insulating mask layer as first sidewall spacers on sidewalls of the first gate electrode;
(4) etching the semiconductor substrate in the n-channel field effect transistor region by using the first insulating mask layer, the first sidewall spacers and the first gate electrode as an etching mask, to form first recesses;
(5) epitaxially growing source/drain regions of a second semiconductor material different from the first semiconductor material, in the first recesses;
(6) after epitaxially growing source/drain regions of the second semiconductor material, removing the first insulating mask layer and the first sidewall spacers;
(7) after removing the first insulating mask layer and the first sidewall spacers, forming second sidewall spacers of an insulating material on sidewalls of the first gate electrode and the second gate electrode;
(8) after forming the second sidewall spacers, forming a second insulating mask layer covering the n-channel field effect transistor region;
(9) etching the semiconductor substrate in the p-channel field effect transistor region by using the second insulating mask layer, the second sidewall spacers, and the second gate electrode, as an etching mask, to form second recesses; and
(10) epitaxially growing source/drain regions of a third semiconductor material different from the first semiconductor material, in the second recesses.
2. The method of manufacturing a semiconductor device according to claim 1 , wherein at least one of said steps (4) and (9) includes an anisotropical etching process and an isotropical etching process following the anisotropical etching process.
3. The method of manufacturing a semiconductor device according to claim 1 , further comprising between said steps (6) and (8) a step of implanting impurity ions into said one and other field effect transistor regions.
4. The method of manufacturing a semiconductor device according to claim 1 , wherein said step (5) epitaxially grows the second semiconductor material containing Si and C at a first temperature, and said step (10) epitaxially grows the third semiconductor material containing Si and Ge at a second temperature lower than said first temperature.
5. The method of manufacturing a semiconductor device according to claim 1 , wherein said first semiconductor is Si, said second semiconductor is Si—C mixed crystal, and said third semiconductor is Si—Ge or Si—Ge—C mixed crystal.
6. The method of manufacturing a semiconductor device according to claim 5 , wherein each of said steps (4) and (9) includes (a) a reactive etching step for Si and (b) a chemical etching process for Si.
7. The method of manufacturing a semiconductor device according to claim 6 , wherein said step (a) etches a depth of 20 to 100 nm and said step (b) etched a depth of 5 to 40 nm.
8. The method of manufacturing a semiconductor device according to claim 6 , wherein said step (a) uses HBr as etchant.
9. The method of manufacturing a semiconductor device according to claim 6 , wherein said step (b) etches at 600 to 900° C. using HCl or Cl 2 as etchant.
10. The method of manufacturing a semiconductor device according to claim 4 , wherein said step (5) is performed by low pressure thermal CVD using silane gas as Si source gas and SiH 3 (CH 3 ) as C source gas.
11. The method of manufacturing a semiconductor device according to claim 4 , wherein said step (10) is performed by low pressure thermal CVD using silane gas as Si source gas and GeH 4 as Ge source gas.
12. The method of manufacturing a semiconductor device according to claim 1 , wherein said step (7) includes a step of depositing a silicon oxide film by thermal CVD using BTBAS and O 2 as source gasses.