IP Library Granted Patent US 8,227,848
Granted Patent B2
US 8,227,848 · App. 12/461,136 · Granted Jul 24, 2012

Semiconductor device

Assignee: Fujitsu Semiconductor Limited
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,227,848
App. No.
12/461,136
Granted
Jul 24, 2012
Kind
B2
Abstract

A substrate is provided with a first wiring layer 111 , an interlayer insulating film 132 on the first wiring layer 111 , a hole 112 A formed in the interlayer insulating film, a first metal layer 112 covering the hole 112 A, a second metal layer 113 formed in the hole 112 A, a dielectric insulating film 135 on the first metal layer 112 , and second wiring layers 114 - 116 on the dielectric insulating film 135 , wherein the first metal layer 112 constitutes at least part of the lower electrode, an area, facing the lower electrode, of the second wiring layers 114 - 116 constitutes the upper electrode, and a capacitor 160 is constructed of the lower electrode, the dielectric insulating film 135 and the upper electrode P 1.

Claims (9)

1. A semiconductor device comprising:

a first wiring layer formed on a semiconductor substrate;

an interlayer insulating film formed on the first wiring layer;

a hole having an opening in an upper surface of the interlayer insulating film and formed in the interlayer insulating film;

a first metal layer covering an internal surface of the hole;

a second metal layer embedded into the hole covered with the first metal layer;

a third metal layer formed on the interlayer insulating film and connected to the first metal layer and the second metal layer forming a lower electrode of a capacitor;

a dielectric insulating film formed on the third metal layer; and

a second wiring layer formed on the dielectric insulating film forming an upper electrode of the capacitor having the dielectric insulating film pinched between the lower electrode and the upper electrode.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 13, 2020
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR MEMORY SOLUTION LIMITED
Reel/Frame 053195/0249 →
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
CHANGE OF NAME Recorded Jul 9, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024651/0744 →
Priority Claims (1)
JP 2005-285223 · Sep 29, 2005 · national
Continuity (2)
Division 11339701 · Jan 26, 2006
Related Publication 20090294905A1 · Dec 3, 2009