Semiconductor device and a method of manufacturing the same
View Patent ↗In a semiconductor device which includes a split-gate type memory cell having a control gate and a memory gate, a low withstand voltage MISFET and a high withstand voltage MISFET, variations of the threshold voltage of the memory cell are suppressed. A gate insulating film of a control gate is thinner than a gate insulating film of a high withstand voltage MISFET, the control gate is thicker than a gate electrode 14 of the low withstand voltage MISFET and the ratio of thickness of a memory gate with respect to the gate length of the memory gate is larger than 1. The control gate and a gate electrode 15 are formed in a multilayer structure including an electrode material film 8 A and an electrode material layer 8 B, and the gate electrode 14 is a single layer structure formed at the same time as the electrode material film 8 A of the control gate.
1. A semiconductor device, comprising:
a first MISFET including a first gate formed over a principal surface of a semiconductor substrate through a first gate insulating film;
a second MISFET including a second gate which is thicker than the first gate, formed over the principal surface of the semiconductor substrate through a second gate insulating film which is thicker than the first gate insulating film; and
a memory cell including a control gate formed over the principal surface of the semiconductor substrate through a third gate insulating film, a charge storage layer having one part thereof formed at one sidewall of the control gate and another part thereof formed over the principal surface of the semiconductor substrate, and a memory gate which is electrically separated from the control gate through the one part of the charge storage layer, as well as electrically separated from the semiconductor substrate through the other part of the charge storage layer, forming a split gate together with the control gate,
wherein the third gate insulating film is thinner than the second gate insulating film, the control gate is thicker than the first gate and the ratio of height of the memory gate with respect to the gate length of the memory gate is larger than 1,
wherein the control gate and the second gate are formed in a multilayer structure including a first electrode material film and a second electrode material film formed over the first electrode material film, and
wherein the first gate is a single layer structure including a first electrode material film of the control gate.
2. The semiconductor device according to claim 1 ,
wherein the third gate insulating film is formed with the first gate insulating film by oxidizing the principal surface of the semiconductor substrate.
3. The semiconductor device according to claim 1 ,
wherein the memory cell further includes a first semiconductor region formed over the principal surface of the semiconductor substrate by ion implantation of a first impurity, using the split gate as a mask, a sidewall portion formed at a sidewall of the memory gate opposite from the one part of the charge storage layer, and a second semiconductor region formed over the principal surface of the semiconductor substrate by ion implantation of a second impurity, using the split gate and the sidewall portion as masks, the second semiconductor region having higher impurity concentration than the first semiconductor region.
4. The semiconductor device according to claim 3 ,
wherein the semiconductor substrate is made of a silicon substrate,
wherein the memory cell further includes a spacer formed at a sidewall of the split gate through the sidewall portion formed at the sidewall of the memory gate, and a silicide layer formed over the second semiconductor region, one end of the silicide layer being arranged in a vicinity of the spacer, and
wherein the silicide layer is not formed over the first semiconductor region.