IP Library Granted Patent US 7,994,012
Granted Patent B2
US 7,994,012 · App. 12/495,957 · Granted Aug 9, 2011

Semiconductor device and a method of manufacturing the same

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Quick Facts
Patent No.
US 7,994,012
App. No.
12/495,957
Granted
Aug 9, 2011
Kind
B2
Abstract

To improve characteristics of a semiconductor device having a nonvolatile memory. There is provided a semiconductor device having a nonvolatile memory cell that performs memory operations by transferring a charge to/from a charge storage film, wherein the nonvolatile memory cell includes a p well formed in a principal plane of a silicon substrate, and a memory gate electrode formed over the principal plane across the charge storage film, and wherein a memory channel region located beneath the charge storage film of the principal plane of the silicon substrate contains fluorine.

Claims (47)

1. A method of manufacturing a semiconductor device, comprising a step of forming a plurality of nonvolatile memory cells in a principal plane of a semiconductor substrate,

wherein the step of forming the nonvolatile memory cells includes the steps of:

(a) forming a first semiconductor region of a first conductivity type in the principal plane of the semiconductor substrate;

(b) forming a memory gate electrode across a charge storage film at a position included in the first semiconductor region in a planar view, over the principal plane of the semiconductor substrate; and

(c) implanting fluorine into a channel region of the principal plane of the semiconductor substrate by first ion implantation, and then activating the fluorine by a first heat treatment,

wherein the channel region is a region located beneath the charge storage film that is formed in the step (b), of the principal plane of the semiconductor substrate, wherein

the step (c) is performed at least after the step (a) is finished, and

wherein the nonvolatile memory cell performs memory operations by transferring a charge to/from the charge storage film.

2. The method of manufacturing a semiconductor device according to claim 1 ,

wherein in the first ion implantation of the step (c), fluorine is implanted into the channel region with a dosage of 1×10 13 to 1×10 15 cm −2 .

3. The method of manufacturing a semiconductor device according to claim 2 ,

wherein the step (b) forms a first insulating film, a second insulating film, and a third insulating film sequentially as the charge storage film,

wherein the second insulating film is an insulating film having a function to trap a charge, and the first and third insulating films sandwiching the second insulating film are insulating films having a function to prevent a charge trapped by the second insulating film from leaking to the outside, and

wherein silicon oxide based insulating films are formed as the first and third insulating films.

4. The method of manufacturing a semiconductor device according to claim 3 ,

wherein the first ion implantation of the step (c) is performed after the step (a) is finished and before the step (b).

5. The method of manufacturing a semiconductor device according to claim 4 ,

wherein the step (b) forms the first insulating film by thermally oxidizing the semiconductor substrate, and

wherein the first heat treatment of the step (c) is performed in the same step as that of the thermal oxidation for forming the first insulating film in the step (b).

6. The method of manufacturing a semiconductor device according to claim 3 ,

wherein the step (b) includes the steps of:

(b1) forming a memory gate conductive film over the principal plane of the semiconductor substrate across the charge storage film; and (b2) forming the memory gate electrode by processing the memory gate conductive film, and

wherein the first ion implantation of the step (c) is performed after the step (b1) and before the step (b2).

7. The method of manufacturing a semiconductor device according to claim 3 ,

wherein the step of forming the nonvolatile memory cell further includes the step of (d) forming a second semiconductor region of a second conductivity type, which is an opposite conductivity type of the first conductivity type, in the principal plane of the semiconductor substrate in the first semiconductor region, of a lateral lower part of the memory gate electrode,

wherein the step (d) forms the second semiconductor region by ion-implanting an impurity to be a second conductivity type into the principal plane of the corresponding semiconductor substrate, and performing a heat treatment, and

wherein the first ion implantation of the step (c) is performed immediately before or immediately after the ion implantation for forming the second semiconductor region in the step (d).

8. The method of manufacturing a semiconductor device according to claim 7 ,

wherein the first heat treatment of the step (c) is performed in the same step as that of the heat treatment for forming the second semiconductor region in the step (d).

9. The method of manufacturing a semiconductor device according to claim 3 ,

wherein the step of forming the nonvolatile memory cell further includes the steps of:

(d) forming a second semiconductor region of the second conductivity type, which is an opposite conductivity type of the first conductivity type, in the principal plane of the semiconductor substrate in the first semiconductor region, of a lateral lower part of the memory gate electrode; and

(e) forming a third semiconductor region of the second conductivity type in the principal plane of the semiconductor substrate in the first semiconductor region and also outside the second semiconductor region in a planar view, of a lateral lower part of the memory gate electrode,

wherein the steps (d) and (e) form the second and third semiconductor regions respectively so that an impurity concentration of the second conductivity type of the third semiconductor region may be higher than that of the second conductivity type of the second semiconductor region,

wherein the step (e) forms the third semiconductor region by implanting an impurity ion to be a second conductivity type into the principal plane of the corresponding semiconductor substrate, and performing a heat treatment, and

wherein the first ion implantation of the step (c) is performed immediately before or immediately after the ion implantation for forming the second semiconductor region in the step (e).

10. The method of manufacturing a semiconductor device according to claim 9 ,

wherein the first heat treatment of the step (c) is performed in the same step as that of the heat treatment for forming the third semiconductor region in the step (e).

11. The method of manufacturing a semiconductor device according to claim 3 ,

wherein the step of forming the nonvolatile memory cell further includes the step of, after the step (a) and before the step (b), (d) forming a control gate electrode across a control gate insulating film at a position included in the first semiconductor region in a planar view, over the principal plane of the semiconductor substrate,

wherein the step (d) forms a silicon oxide based insulating film as the control gate insulating film, and

wherein the step (b) forms the memory gate electrode across the charge storage film so as to be adjacent to the control gate electrode formed in the step (d).

12. The method of manufacturing a semiconductor device according to claim 11 ,

wherein the first ion implantation of the step (c) is performed after the step (a) is finished and before the step (d).

13. The method of manufacturing a semiconductor device according to claim 12 ,

wherein the step (d) forms the control gate insulating film by thermally oxidizing the semiconductor substrate, and

wherein the first heat treatment of the step (c) is performed in the same step as that of the thermal oxidation for forming the control gate insulating film in the step (d).

Assignments (4)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
CHANGE OF NAME Recorded Aug 13, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 024864/0635 →
MERGER Recorded Aug 13, 2010
From: RENESAS TECHNOLOGY CORP.
To: NEC ELECTRONICS CORPORATION
Reel/Frame 024879/0190 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2009
From: SHIBA, KAZUYOSHI
To: RENESAS TECHNOLOGY CORP.
Reel/Frame 022906/0932 →