Semiconductor device and fabricating method thereof

1. A semiconductor device, comprising:

a memory cell transistor which has a floating gate formed over a semiconductor substrate via a tunnel insulating film, a control gate formed over the floating gate via an insulating film, and a source and a drain formed in the semiconductor substrate on both sides of the floating gate via a channel area; and

a selecting transistor which has a select gate formed over the semiconductor substrate via a gate insulating film, and a source and a drain formed in the semiconductor substrate on both sides of the select gate, wherein

the source of the selecting transistor is connected to the drain of the memory cell transistor,

the source of the memory cell transistor has an N-type first impurity diffusion layer, an N-type second impurity diffusion layer deeper than the N-type first impurity diffusion layer, and an N-type third impurity diffusion layer which is formed in the N-type second impurity diffusion layer and is shallower than the N-type second impurity diffusion layer,

wherein the end of the N-type first impurity diffusion layer on a side of which the floating gate is formed being positioned between an end portion of the N-type second impurity diffusion layer on the side of which the floating gate is formed and the channel area, and

an impurity concentration of the N-type second impurity diffusion layer is lower than the impurity concentration of the third impurity diffusion layer.

2. The semiconductor device according to claim 1 , further comprising:

a memory cell array in which a plurality of memory cells having the memory cell transistor and the selecting transistor are arranged in a matrix pattern;

a plurality of bit lines, each of which commonly connects the drains of the plurality of selecting transistors present on a same column;

a plurality of first word lines, each of which commonly connects the control gates of the plurality of memory cell transistors present on a same row;

a plurality of second word lines, each of which commonly connects the select gates of the plurality of selecting transistors present on a same row; and

a plurality of source lines, each of which commonly connects the sources of the plurality of memory cell transistors present on a same row.

3. The semiconductor device according to claim 1 , further comprising:

a P-type pocket area which is shallower than the N-type first impurity diffusion layer and is formed on the N-type first impurity diffusion layer on a side of which the channel area is formed.

4. The semiconductor device according to claim 1 , wherein

the end portion of the N-type first impurity diffusion layer on the side of which the floating gate is positioned within an area below the floating gate.

5. The semiconductor device according to claim 1 , wherein

the impurity concentration in a portion of the N-type second impurity diffusion layer deeper than the N-type third impurity diffusion layer is lower than impurity concentration in the end portion of the N-type first impurity diffusion layer on a side of which the channel area is formed.

6. The semiconductor device according to claim 1 , wherein

the end portion of the N-type first impurity diffusion layer on a side of which the floating gate is formed is positioned between an end portion of the N-type second impurity diffusion layer on the side of which the floating gate is formed and a side of which the channel area is formed.

7. The semiconductor device according to claim 1 , wherein

the N-type first impurity diffusion layer has the same depth as that of a fourth impurity diffusion layer forming the drain of the memory cell transistor.

8. The semiconductor device according to claim 7 , wherein the source of the selecting transistor is formed by the fourth impurity diffusion layer.

9. The semiconductor device according to claim 1 , wherein

the source of the selecting transistor and the drain of the memory cell transistor are formed integrally by one impurity diffusion layer.