Semiconductor integrated circuit device
View Patent ↗To provide a technique that can maintain uniformity of semiconductor elements and wirings microfabricated, while maintaining the mounting efficiency of circuit cells onto a chip. Respective gate electrodes of an n-channel type MISFET and another n-channel type MISFET forming a NAND circuit cell are coupled to the same node, and simultaneously perform respective on-off operations according to the same input signal. These n-channel type MISFETs are arranged adjacent to each other, and electrically coupled in series. Respective gate electrodes of a p-channel type MISFET and another p-channel type MISFET forming the NAND circuit cell are coupled to the same node, and simultaneously perform respective on-off operations according to the same input signal. These p-channel type MISFETs are arranged adjacent to each other, and electrically coupled in series.
1. A semiconductor integrated circuit device comprising:
a circuit cell including a plurality of MISFETs of the same channel type having gates formed over a main surface of a semiconductor substrate to be coupled to the same node,
wherein the plurality of MISFETs are each coupled adjacent to each other in series, and perform respective on-off operations in cooperation with input of a signal into the node,
wherein a gate length of each of the MISFETs is equal to or less than 65 nm, and
wherein adjacent gate electrodes of the MISFETs are arranged to be spaced apart from each other within a range that is five to fifteen times as long as the gate length.
2. The semiconductor integrated circuit device according to claim 1 , wherein a number of said plurality of MISFETS is two.
3. The semiconductor integrated circuit device according to claim 2 , wherein the signal into the node is a signal whose rate is hardly degraded.
4. The semiconductor integrated circuit device according to claim 3 , wherein the signal into the node is a SCAN signal, a RESET signal, or a SET signal.
5. A semiconductor integrated circuit device comprising:
a circuit cell including a plurality of MISFETs of the same channel type having gates formed over a main surface of a semiconductor substrate to be coupled to the same node,
wherein the plurality of MISFETs are each coupled adjacent to each other in series, and perform respective on-off operations in cooperation with input of a signal into the node,
wherein a gate length of each of the MISFETs is equal to or less than 45 nm, and
wherein adjacent gate electrodes of the MISFETs are arranged to be spaced apart from each other within a range that is three to ten times as long as the gate length.
6. The semiconductor integrated device according to claim 1 , wherein the MISFETs form a full adder circuit, a half adder circuit, a flip-flop circuit with set, a flip-flop circuit with reset, a flip-flop circuit with scanning, a 4-input selector circuit, a 3-input selector circuit, or a composite circuit comprised of twenty to thirty transistors including the MISFETs.
7. The semiconductor integrated circuit device according to claim 1 , wherein the circuit cell is formed only of a group of the transistors including the MISFETs, and a lowermost layer wiring over the main surface of the semiconductor substrate.
8. The semiconductor integrated circuit device according to claim 5 , wherein a number of said plurality of MISFETs is two.
9. The semiconductor integrated circuit device according to claim 8 ,
wherein the signal into the node is a signal whose rate is hardly degraded.
10. The semiconductor integrated circuit device according to claim 9 ,
wherein the signal into the node is a SCAN signal, a RESET signal, or a SET signal.
11. The semiconductor integrated device according to claim 5 ,
wherein the MISFETs form a full adder circuit, a half adder circuit, a flip-flop circuit with set, a flip-flop circuit with reset, a flip-flop circuit with scanning, a 4-input selector circuit, a 3-input selector circuit, or a composite circuit comprised of twenty to thirty transistors including the MISFETs.
12. The semiconductor integrated circuit device according to claim 5 ,
wherein the circuit cell is formed only of a group of the transistors including the MISFETs, and a lowermost layer wiring over the main surface of the semiconductor substrate.