Method of manufacturing a semiconductor device including epitaxially growing semiconductor epitaxial layers on a surface of semiconductor substrate
A semiconductor device has a first MOS transistor formed on first active region of the first conductivity type, having first gate electrode structure, first source/drain regions, recesses formed in the first source/drain regions, and semiconductor buried regions buried and grown on the recesses for applying stress to the channel under the first gate electrode structure, and a second MOS transistor formed on second active region of the second conductivity type, having second gate electrode structure, second source/drain regions, and semiconductor epitaxial layers formed on the second source/drain regions without forming recesses and preferably applying stress to the channel under the second gate electrode structure. In a CMOS device, performance can be improved by utilizing stress and manufacture processes can be simplified.
1. A semiconductor device comprising:
a semiconductor substrate including a first active region of a first conductivity type, a second active region of a second conductivity type, and an isolation region;
a first MOS transistor including a first gate electrode structure formed on said first active region, first source/drain regions of the second conductivity type formed in said first active region on both sides of said first gate electrode structure, a first channel region under said first gate electrode structure, recesses dug from surfaces of said first source/drain regions, and semiconductor buried regions of the second conductivity type formed in said recesses and applying stress to the first channel region, said semiconductor buried regions having surfaces at a level higher than a surface of said semiconductor substrate;
a second MOS transistor including a second gate electrode structure formed on said second active region, second source/drain regions of the first conductivity type formed in said second active region on both sides of said second gate electrode structure, a second channel region under said second gate electrode structure, semiconductor epitaxial layers of the first conductivity type formed on said second source/drain regions without involvement of recesses;
first source/drain extension regions formed in said first active region on both sides of said first gate electrode structure and between said first source/drain regions and the first channel region;
second source/drain extension regions formed in said second active region on both sides of said second gate electrode structure and between said second source/drain regions and the second channel region;
first side wall spacers formed on side walls of said first gate electrode structure and formed above said first source/drain extension regions;
second side wall spacers formed on side walls of said second gate electrode structure and formed above said second source/drain extension regions;
third side wall spacers formed on said first side wall spacers and partially covering said semiconductor buried regions;
fourth side wall spacers formed on said second side wall spacers and partially covering said semiconductor epitaxial layers; and
silicide regions formed on said semiconductor buried regions not covered with said third side wall spacers and on said semiconductor epitaxial layers not covered with said fourth side wall spacers,
wherein said semiconductor buried regions are formed between said first source/drain extension regions and the isolation region.
2. The semiconductor device according to claim 1 , wherein said semiconductor buried regions are made of Si—Ge or C-doped Si.
3. The semiconductor device according to claim 2 , wherein the first conductivity type is n-type, the second conductivity type is p-type, said semiconductor buried regions are made of Si—Ge, and said semiconductor epitaxial layers are made of C-doped Si or Si.
4. The semiconductor device according to claim 2 , wherein the first conductivity type is p-type, the second conductivity type is n-type, said semiconductor buried regions are made of C-doped Si, and said semiconductor epitaxial layers are made of Si—Ge or Si.
5. The semiconductor device according to claim 1 , wherein:
said semiconductor epitaxial layers each include a first portion having a first thickness and formed in a region near said second gate electrode structure and a second portion having a second thickness thicker than said first thickness and formed in a region remote from said second gate electrode structure; and
the semiconductor device further comprises additional semiconductor epitaxial layers formed on said first active region on said first gate electrode structure side of said semiconductor buried regions, said additional semiconductor epitaxial layers each having a same composition as a composition of said semiconductor epitaxial layers formed on said second active region and a same thickness as said first thickness.
6. The semiconductor device according to claim 5 , wherein said first portion of said semiconductor epitaxial layers are disposed under said second side wall spacers, and said additional epitaxial layers are disposed under said first side wall spacers.
7. The semiconductor device according to claim 1 , wherein the second gate electrode structure includes a gate insulating film formed on the second active region and a gate electrode formed on the gate insulating film, and the silicide layers have bottom surfaces at a level higher than a bottom surface of the gate insulating film.