Manufacturing method of a MOS transistor using a sidewall spacer
A method of manufacturing a semiconductor device which includes forming first and second gate patterns, forming first and second sidewall spacers on sidewalls of the first and second gate patterns respectively, implanting a first impurity into the semiconductor substrate, forming a third sidewall spacer on the first sidewall spacer and a fourth sidewall spacer on the second sidewall spacer in such a manner that the third sidewall spacer is in contact with the fourth sidewall spacer between the first and second gate patterns, implanting a second impurity into the semiconductor substrate, and removing the third and the fourth sidewall spacers.
1. A method of manufacturing a semiconductor device comprising:
forming a first gate pattern and a second gate pattern adjacent to the first gate pattern over a semiconductor substrate;
forming a first sidewall spacer on a sidewall of the first gate pattern and a second sidewall spacer on a sidewall of the second gate pattern;
implanting a first impurity into the semiconductor substrate using the first gate pattern, the first sidewall spacer, the second gate pattern, and the second sidewall spacer as a mask;
forming a first insulating film covering the first gate pattern, the first sidewall spacer, the second gate pattern, and the second sidewall spacer;
etching the first insulating film to expose the semiconductor substrate and to form a third sidewall spacer on a side surface of the first sidewall spacer and a fourth sidewall spacer on a side surface of the second sidewall spacer in such a manner that the third sidewall spacer is in contact with the fourth sidewall spacer between the first gate pattern and second gate pattern;
implanting a second impurity into the semiconductor substrate using the first gate pattern, the first sidewall spacer, the third sidewall spacer, the second gate pattern, the second sidewall spacer, and the fourth sidewall spacer as a mask to form a first region being deeper than a second region provided under a contact portion between the third sidewall spacer and the fourth sidewall spacer; and
after the implantation of the second impurity, removing the third sidewall spacer and the fourth sidewall spacer.
2. The method according to claim 1 , further comprising:
before forming the first sidewall spacer and second sidewall spacer, implanting a third impurity into the semiconductor substrate using the first gate pattern and the second gate pattern as a mask.
3. The method according to claim 2 , wherein the first impurity is implanted shallower than the second impurity implanted and deeper than the third impurity implanted.
4. The method according to claim 2 , further comprising:
after removing the third sidewall spacer and the fourth sidewall spacer, forming a silicide over a surface of the semiconductor substrate.
5. The method according to claim 1 , wherein the contact portion between the third sidewall spacer and the fourth sidewall spacer does not have a flat portion.