Semiconductor integrated circuit device and a method of manufacturing the same
View Patent ↗To provide a circuit layout design method that can prevent degradation of the circuit reliability even in highly miniaturized circuit cells. In order to prevent noise from a power supply potential or a reference potential with a large potential difference from affecting a gate electrode and causing a malfunction, a first plug connected to the gate electrode and a second plug to which the power supply potential or the reference potential is supplied are required to be spaced from each other by a distance sufficient for the noise from the power supply potential or the reference potential not to affect the first plug. To this end, among the second plugs placed at equal intervals under the wiring, only the second plug placed at a layout position that is not sufficiently spaced from the first plug is deleted at the time of planar layout design.
1. A method of manufacturing a semiconductor integrated circuit device having an integrated circuit, the method comprising the steps of:
(a) preparing a first layout of the integrated circuit including a plurality of active regions, a plurality of gate electrodes, a plurality of signaling wirings, a plurality of power-feeding wirings, a plurality of signaling plugs, and a plurality of power-feeding plugs; and
(b) deleting the power-feeding plug that is placed within a first distance from each of the signaling plugs among the power-feeding plugs from the first layout,
wherein in the step (a), the power-feeding plugs for electrically connecting the power-feeding wiring to the active region are placed under the power-feeding wiring,
wherein a potential higher than that of the signaling wiring and the signaling plug is supplied to the power-feeding wiring and the power-feeding plug, and
wherein the power-feeding plug deleted from the first layout in the step (b) is close to the signaling plug, close enough to impair an operation of the integrated circuit.
2. The method of manufacturing a semiconductor integrated circuit device according to claim 1 ,
wherein the first distance is 1.5 times a diameter of the signaling plug.
3. The method of manufacturing a semiconductor integrated circuit device according to claim 2 ,
wherein in the step (a), the power-feeding plugs are placed at equal intervals under the power-feeding wirings.
4. The method of manufacturing a semiconductor integrated circuit device according to claim 2 ,
wherein the integrated circuit is formed from one or more circuit cells, and
wherein the step (a) and the step (b) are performed on each of the circuit cells.
5. The method of manufacturing a semiconductor integrated circuit device according to claim 4 ,
wherein the power-feeding wiring and the power-feeding plug are arranged between two adjacent circuit cells and are commonly included in the first layout of both of the two adjacent circuit cells; and
wherein in the step (b), an identification mark is placed at a position of the power-feeding plug that has been deleted from the first layout, and the method further comprising the step of
(c) forming a second layout of the integrated circuit by arranging each of the first layouts of the circuit cells, and then deleting the power-feeding plug at a position where the power-feeding plug is overlapped with the identification mark, from the second layout.
6. The method of manufacturing a semiconductor integrated circuit device according to claim 5 ,
wherein the second layout is a layout of an entire semiconductor chip, and
wherein a mask for transferring a pattern of the integrated circuit is manufactured based on the second layout.
7. The method of manufacturing a semiconductor integrated circuit device according to claim 2 ,
wherein the first layout is formed within such a small planar region that the power-feeding plug to be deleted in the step (b) cannot be formed spaced by at least the first distance from the closest signaling plug.
8. The method of manufacturing a semiconductor integrated circuit device according to claim 2 ,
wherein the first layout reduces a planar size of a semiconductor chip having the integrated circuit, in a direction intersecting an extending direction of the power-feeding wirings.