IP Library Granted Patent US 7,865,814
Granted Patent B2
US 7,865,814 · App. 12/547,921 · Granted Jan 4, 2011

Path metric difference computation unit for computing path differences through a multiple-step trellis

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,865,814
App. No.
12/547,921
Filed
Aug 26, 2009
Granted
Jan 4, 2011
Kind
B2
Art Unit
2112
USPC
714/792
Abstract

A path metric difference computation unit is disclosed for computing path differences through a multiple-step trellis. Path differences are computed between paths through a multiple-step trellis, wherein a first path is a winning path for each single-step-trellis period of a multiple-step-trellis cycle, a second path is a winning path for a first single-step-trellis period and is a losing path for a second single-step-trellis period and a third path is a losing path for a first single-step-trellis period and is a winning path for a second single-step-trellis period. The disclosed path metric difference computation unit comprises path metric difference generators for generating a path metric difference Δ 0 for a second single-step-trellis period based on a difference between the first path and the second path, and a path metric difference Δ −1 for a first single-step-trellis period based on a difference between the first path and the third path, wherein intermediate path metric values or intermediate path metric difference values are reused to generate the path metric differences Δ 0 or Δ −1 .

Claims (21)

1. A path metric difference computation unit for computing differences between paths through a multiple-step trellis, wherein a first of said plurality of paths is a winning path for each single-step-trellis period of a multiple-step-trellis cycle, a second of said plurality of paths is a winning path for a first single-step-trellis period and is a losing path for a second single-step-trellis period of the multiple-step-trellis cycle and a third of said plurality of paths is a losing path for the first single-step-trellis period and is a winning path for the second single-step-trellis period of the multiple-step-trellis cycle, comprising:

one or more path metric difference generators for generating a path metric difference Δ 0 for the second single-step-trellis period of the multiple-step-trellis cycle based on a difference between the first path and the second path, and a path metric difference Δ −1 for the first single-step-trellis period of the multiple-step-trellis cycle based on a difference between the first path and the third path, wherein one or more of intermediate path metric values and intermediate path metric difference values are reused to generate one or more of said path metric differences Δ 0 and Δ −1 .

2. The path metric difference computation unit of claim 1 , further comprising a comparator to compare path metrics of said second path and a fourth path to identify said second path and a subtractor to determine said path metric difference Δ 0 between the first and second paths.

3. The path metric difference computation unit of claim 2 , wherein an output of said comparator is a selection signal, F.

4. The path metric difference computation unit of claim 3 , wherein said selection signal, F, is used to compute equivalence bits in a path metric comparison unit.

5. The path metric difference computation unit of claim 2 , further comprising a selector to select between said path metrics of said second and fourth paths to identify said second path based on a selection signal.

6. The path metric difference computation unit of claim 2 , wherein each of said path metrics of said second path and said fourth path are selected from a plurality of newly computed path metrics.

7. The path metric difference computation unit of claim 1 , further comprising a subtractor to determine said path metric difference Δ −1 between the first and third paths.

8. The path metric difference computation unit of claim 7 , wherein the path metric of said third path is selected from a plurality of newly computed path metrics.

9. The path metric difference computation unit of claim 1 , further comprising one or more pipeline registers and wherein said first path is determined in a first multiple-step-trellis cycle and said path metric differences are generated in a subsequent multiple-step-trellis cycle.

10. The path metric difference computation unit of claim 1 , further comprising a comparator for determining a path metric for said first path into a state by comparing path metrics for path extensions into said state.

11. The path metric difference computation unit of claim 1 , further comprising one or more adders, comparators and selectors to perform an add-compare-select operation for a state to determine said first path.

12. The path metric difference computation unit of claim 11 , wherein the newly computed path metrics obtained from said add-compare select operation are reused to generate the one or more of said path metric differences Δ 0 and Δ −1 .

13. The path metric difference computation unit of claim 1 , further comprising a plurality of comparators for computing path metric differences between a plurality of paths into a given state.

14. The path metric difference computation unit of claim 13 , further comprising a selector to determine the first path based on outputs of said plurality of comparators.

15. The path metric difference computation unit of claim 14 , wherein the path metric differences used to determine the first path are reused to generate the one or more of said path metric differences Δ 0 and Δ −1 .

16. The path metric difference computation unit of claim 1 , further comprising a selector to select said path metric difference Δ −1 based on one or more selection signals.

17. The path metric difference computation unit of claim 1 , further comprising a comparator that compares the path metric difference between said first path and said second path and the path metric difference between said first path and a path that is a losing path for said first and second single-step-trellis periods of a multiple-step-trellis cycle to generate a selection signal F.

18. The path metric difference computation unit of claim 17 , wherein said selection signal, F, is used to compute equivalence bits in a path metric comparison unit.

19. The path metric difference computation unit of claim 1 , further comprising a selector to select said path metric difference Δ 0 based on one or more selection signals.

20. The path metric difference computation unit of claim 1 , wherein said path metric differences Δ 0 and Δ −1 are used to compute reliabilities in a reliability unit.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
To: BROADCOM INTERNATIONAL PTE. LTD.
Reel/Frame 053771/0901 →
CORRECTIVE ASSIGNMENT TO CORRECT THE PROPERTY NUMBERS PREVIOUSLY RECORDED AT REEL: 47630 FRAME: 344. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 21, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0267 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 9/5/2018 PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0687. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0344 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0687 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →