IP Library Granted Patent US 7,927,946
Granted Patent B2
US 7,927,946 · App. 12/563,382 · Granted Apr 19, 2011

Semiconductor device and manufacturing method of the same

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Quick Facts
Patent No.
US 7,927,946
App. No.
12/563,382
Granted
Apr 19, 2011
Kind
B2
Abstract

An interlayer insulating film ( 14 ) covering a ferroelectric capacitor is formed and a contact hole ( 19 ) reaching a top electrode ( 11 a ) is formed in the interlayer insulating film ( 14 ). An Al wiring ( 17 ) connected to the top electrode ( 11 a ) via the contact hole ( 19 ) is formed on the interlayer insulating film ( 14 ). A planar shape of the contact hole ( 19 ) is an ellipse.

Claims (12)

1. A manufacturing method of a semiconductor device, comprising the steps of:

forming a ferroelectric capacitor above a semiconductor substrate;

forming an interlayer insulating film covering the ferroelectric capacitor;

forming a hole reaching a top electrode of the ferroelectric capacitor in the interlayer insulating film; and

forming a wiring connected to the top electrode via the hole on the interlayer insulating film,

wherein, in said step of forming the hole, a planar shape of the hole is set to a shape in which lengths of two axes orthogonal to each other are different, and

wherein a direction in which a major axis of the hole is extending is set to a direction corresponding to a direction in which a long side of the top electrode is extending.

2. The manufacturing method of a semiconductor device according to claim 1 , wherein the planar shape of the hole is set to an ellipse.

3. The manufacturing method of a semiconductor device according to claim 1 , wherein the planar shape of the hole is set to a rectangle.

4. The manufacturing method of a semiconductor device according to claim 1 , wherein the planar shape of the hole is set to a shape in which four corners of a rectangle are rounded off

5. The manufacturing method of a semiconductor device according to claim 1 , wherein said step of forming the ferroelectric capacitor includes the step of forming a ferroelectric film containing Pb, Zr, and Ti, and a conductive film containing Ir is formed as the top electrode.

6. The manufacturing method of a semiconductor device according to claim 1 , wherein both lengths of the major axis and minor axis of the hole are set to ranges of respective displacement margins which are set for a top electrode.

Assignments (2)
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
CHANGE OF NAME Recorded Jul 9, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024651/0744 →